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75dd0a8f3d
We detect i586 and i686 features at run-time by checking CX8 and CMOV CPUID features bits. We can use these information to select the best implementation in ix86 multiarch. HAS_I586/HAS_I686 is true if i586/i686 instructions are available on the processor. Due to the reordering and the other nifty extensions in i686, it is not really good to use heavily i586 optimized code on an i686. It's better to use i486 code if it isn't an i586. USE_I586/USE_I686 is true if i586/i686 implementation should be used for the processor. USE_I586 is true only if i686 instructions aren't available. If i686 instructions are available, we always choose i686 or i486 implementation, in that order, and we never choose i586 implementation for i686-class processors. * sysdeps/i386/init-arch.h: New file. * sysdeps/i386/i586/init-arch.h: Likewise. * sysdeps/i386/i686/init-arch.h: Likewise. * sysdeps/x86/cpu-features.c (init_cpu_features): Set bit_I586 bit if CX8 is available. Set bit_I686 bit if CMOV is available. * sysdeps/x86/cpu-features.h (bit_I586): New. (bit_I686): Likewise. (bit_CX8): Likewise. (bit_CMOV): Likewise. (index_CX8): Likewise. (index_CMOV): Likewise. (index_I586): Likewise. (index_I686): Likewise. (reg_CX8): Likewise. (reg_CMOV): Likewise. (HAS_I586): Defined as HAS_ARCH_FEATURE (I586) if i586 isn't available at compile-time. (HAS_I686): Defined as HAS_ARCH_FEATURE (I686) if i686 isn't available at compile-time. * sysdeps/x86/init-arch.h (USE_I586): New macro. (USE_I686): Likewise.
223 lines
6.9 KiB
C
223 lines
6.9 KiB
C
/* Initialize CPU feature data.
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This file is part of the GNU C Library.
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Copyright (C) 2008-2015 Free Software Foundation, Inc.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <cpuid.h>
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#include <cpu-features.h>
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static inline void
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get_common_indeces (struct cpu_features *cpu_features,
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unsigned int *family, unsigned int *model)
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{
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unsigned int eax;
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__cpuid (1, eax, cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_1].edx);
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GLRO(dl_x86_cpu_features).cpuid[COMMON_CPUID_INDEX_1].eax = eax;
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*family = (eax >> 8) & 0x0f;
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*model = (eax >> 4) & 0x0f;
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}
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static inline void
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init_cpu_features (struct cpu_features *cpu_features)
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{
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unsigned int ebx, ecx, edx;
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unsigned int family = 0;
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unsigned int model = 0;
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enum cpu_features_kind kind;
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#if !HAS_CPUID
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if (__get_cpuid_max (0, 0) == 0)
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{
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kind = arch_kind_other;
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goto no_cpuid;
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}
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#endif
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__cpuid (0, cpu_features->max_cpuid, ebx, ecx, edx);
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/* This spells out "GenuineIntel". */
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if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
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{
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kind = arch_kind_intel;
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get_common_indeces (cpu_features, &family, &model);
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unsigned int eax = cpu_features->cpuid[COMMON_CPUID_INDEX_1].eax;
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unsigned int extended_family = (eax >> 20) & 0xff;
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unsigned int extended_model = (eax >> 12) & 0xf0;
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if (family == 0x0f)
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{
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family += extended_family;
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model += extended_model;
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}
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else if (family == 0x06)
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{
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ecx = cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx;
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model += extended_model;
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switch (model)
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{
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case 0x1c:
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case 0x26:
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/* BSF is slow on Atom. */
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cpu_features->feature[index_Slow_BSF] |= bit_Slow_BSF;
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break;
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case 0x37:
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case 0x4a:
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case 0x4d:
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case 0x5a:
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case 0x5d:
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/* Unaligned load versions are faster than SSSE3
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on Silvermont. */
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#if index_Fast_Unaligned_Load != index_Prefer_PMINUB_for_stringop
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# error index_Fast_Unaligned_Load != index_Prefer_PMINUB_for_stringop
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#endif
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#if index_Fast_Unaligned_Load != index_Slow_SSE4_2
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# error index_Fast_Unaligned_Load != index_Slow_SSE4_2
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#endif
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cpu_features->feature[index_Fast_Unaligned_Load]
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|= (bit_Fast_Unaligned_Load
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| bit_Prefer_PMINUB_for_stringop
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| bit_Slow_SSE4_2);
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break;
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default:
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/* Unknown family 0x06 processors. Assuming this is one
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of Core i3/i5/i7 processors if AVX is available. */
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if ((ecx & bit_AVX) == 0)
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break;
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case 0x1a:
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case 0x1e:
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case 0x1f:
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case 0x25:
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case 0x2c:
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case 0x2e:
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case 0x2f:
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/* Rep string instructions, copy backward, unaligned loads
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and pminub are fast on Intel Core i3, i5 and i7. */
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#if index_Fast_Rep_String != index_Fast_Copy_Backward
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# error index_Fast_Rep_String != index_Fast_Copy_Backward
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#endif
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#if index_Fast_Rep_String != index_Fast_Unaligned_Load
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# error index_Fast_Rep_String != index_Fast_Unaligned_Load
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#endif
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#if index_Fast_Rep_String != index_Prefer_PMINUB_for_stringop
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# error index_Fast_Rep_String != index_Prefer_PMINUB_for_stringop
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#endif
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cpu_features->feature[index_Fast_Rep_String]
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|= (bit_Fast_Rep_String
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| bit_Fast_Copy_Backward
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| bit_Fast_Unaligned_Load
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| bit_Prefer_PMINUB_for_stringop);
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break;
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}
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}
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}
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/* This spells out "AuthenticAMD". */
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else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
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{
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kind = arch_kind_amd;
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get_common_indeces (cpu_features, &family, &model);
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ecx = cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx;
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unsigned int eax;
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__cpuid (0x80000000, eax, ebx, ecx, edx);
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if (eax >= 0x80000001)
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__cpuid (0x80000001,
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cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].eax,
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cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].ebx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].ecx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].edx);
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}
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else
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kind = arch_kind_other;
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/* Support i586 if CX8 is available. */
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if (HAS_CPU_FEATURE (CX8))
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cpu_features->feature[index_I586] |= bit_I586;
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/* Support i686 if CMOV is available. */
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if (HAS_CPU_FEATURE (CMOV))
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cpu_features->feature[index_I686] |= bit_I686;
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if (cpu_features->max_cpuid >= 7)
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__cpuid_count (7, 0,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].eax,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].ebx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].ecx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].edx);
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/* Can we call xgetbv? */
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if (HAS_CPU_FEATURE (OSXSAVE))
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{
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unsigned int xcrlow;
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unsigned int xcrhigh;
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asm ("xgetbv" : "=a" (xcrlow), "=d" (xcrhigh) : "c" (0));
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/* Is YMM and XMM state usable? */
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if ((xcrlow & (bit_YMM_state | bit_XMM_state)) ==
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(bit_YMM_state | bit_XMM_state))
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{
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/* Determine if AVX is usable. */
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if (HAS_CPU_FEATURE (AVX))
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cpu_features->feature[index_AVX_Usable] |= bit_AVX_Usable;
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#if index_AVX2_Usable != index_AVX_Fast_Unaligned_Load
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# error index_AVX2_Usable != index_AVX_Fast_Unaligned_Load
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#endif
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/* Determine if AVX2 is usable. Unaligned load with 256-bit
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AVX registers are faster on processors with AVX2. */
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if (HAS_CPU_FEATURE (AVX2))
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cpu_features->feature[index_AVX2_Usable]
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|= bit_AVX2_Usable | bit_AVX_Fast_Unaligned_Load;
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/* Check if OPMASK state, upper 256-bit of ZMM0-ZMM15 and
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ZMM16-ZMM31 state are enabled. */
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if ((xcrlow & (bit_Opmask_state | bit_ZMM0_15_state
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| bit_ZMM16_31_state)) ==
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(bit_Opmask_state | bit_ZMM0_15_state | bit_ZMM16_31_state))
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{
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/* Determine if AVX512F is usable. */
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if (HAS_CPU_FEATURE (AVX512F))
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{
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cpu_features->feature[index_AVX512F_Usable]
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|= bit_AVX512F_Usable;
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/* Determine if AVX512DQ is usable. */
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if (HAS_CPU_FEATURE (AVX512DQ))
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cpu_features->feature[index_AVX512DQ_Usable]
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|= bit_AVX512DQ_Usable;
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}
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}
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/* Determine if FMA is usable. */
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if (HAS_CPU_FEATURE (FMA))
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cpu_features->feature[index_FMA_Usable] |= bit_FMA_Usable;
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/* Determine if FMA4 is usable. */
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if (HAS_CPU_FEATURE (FMA4))
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cpu_features->feature[index_FMA4_Usable] |= bit_FMA4_Usable;
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}
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}
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#if !HAS_CPUID
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no_cpuid:
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#endif
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cpu_features->family = family;
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cpu_features->model = model;
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cpu_features->kind = kind;
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}
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