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109 lines
3.4 KiB
C
109 lines
3.4 KiB
C
/* 68k FPU control word definitions.
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Copyright (C) 1996-2013 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _FPU_CONTROL_H
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#define _FPU_CONTROL_H
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/*
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* Motorola floating point control register bits.
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*
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* 31-16 -> reserved (read as 0, ignored on write)
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* 15 -> enable trap for BSUN exception
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* 14 -> enable trap for SNAN exception
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* 13 -> enable trap for OPERR exception
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* 12 -> enable trap for OVFL exception
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* 11 -> enable trap for UNFL exception
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* 10 -> enable trap for DZ exception
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* 9 -> enable trap for INEX2 exception (INEX on Coldfire)
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* 8 -> enable trap for INEX1 exception (IDE on Coldfire)
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* 7-6 -> Precision Control (only bit 6 is used on Coldfire)
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* 5-4 -> Rounding Control
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* 3-0 -> zero (read as 0, write as 0)
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*
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*
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* Precision Control:
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* 00 - round to extended precision
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* 01 - round to single precision
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* 10 - round to double precision
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* 11 - undefined
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*
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* Rounding Control:
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* 00 - rounding to nearest (RN)
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* 01 - rounding toward zero (RZ)
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* 10 - rounding (down)toward minus infinity (RM)
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* 11 - rounding (up) toward plus infinity (RP)
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*
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* The hardware default is 0x0000. I choose 0x5400.
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*/
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#include <features.h>
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/* masking of interrupts */
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#define _FPU_MASK_BSUN 0x8000
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#define _FPU_MASK_SNAN 0x4000
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#define _FPU_MASK_OPERR 0x2000
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#define _FPU_MASK_OVFL 0x1000
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#define _FPU_MASK_UNFL 0x0800
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#define _FPU_MASK_DZ 0x0400
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#define _FPU_MASK_INEX1 0x0200
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#define _FPU_MASK_INEX2 0x0100
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/* precision control */
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#ifdef __mcoldfire__
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#define _FPU_DOUBLE 0x00
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#else
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#define _FPU_EXTENDED 0x00 /* RECOMMENDED */
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#define _FPU_DOUBLE 0x80
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#endif
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#define _FPU_SINGLE 0x40 /* DO NOT USE */
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/* rounding control */
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#define _FPU_RC_NEAREST 0x00 /* RECOMMENDED */
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#define _FPU_RC_ZERO 0x10
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#define _FPU_RC_DOWN 0x20
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#define _FPU_RC_UP 0x30
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#ifdef __mcoldfire__
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#define _FPU_RESERVED 0xFFFF800F
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#else
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#define _FPU_RESERVED 0xFFFF000F /* Reserved bits in fpucr */
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#endif
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/* Now two recommended fpucr */
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/* The fdlibm code requires no interrupts for exceptions. Don't
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change the rounding mode, it would break long double I/O! */
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#define _FPU_DEFAULT 0x00000000
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/* IEEE: same as above, but exceptions. We must make it non-zero so
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that __setfpucw works. This bit will be ignored. */
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#define _FPU_IEEE 0x00000001
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/* Type of the control word. */
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typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
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/* Macros for accessing the hardware control word. */
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#define _FPU_GETCW(cw) __asm__ ("fmove%.l %!, %0" : "=dm" (cw))
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#define _FPU_SETCW(cw) __asm__ volatile ("fmove%.l %0, %!" : : "dm" (cw))
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/* Default control word set at startup. */
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extern fpu_control_t __fpu_control;
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#endif /* _M68K_FPU_CONTROL_H */
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