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I used these shell commands: ../glibc/scripts/update-copyrights $PWD/../gnulib/build-aux/update-copyright (cd ../glibc && git commit -am"[this commit message]") and then ignored the output, which consisted lines saying "FOO: warning: copyright statement not found" for each of 7061 files FOO. I then removed trailing white space from math/tgmath.h, support/tst-support-open-dev-null-range.c, and sysdeps/x86_64/multiarch/strlen-vec.S, to work around the following obscure pre-commit check failure diagnostics from Savannah. I don't know why I run into these diagnostics whereas others evidently do not. remote: *** 912-#endif remote: *** 913: remote: *** 914- remote: *** error: lines with trailing whitespace found ... remote: *** error: sysdeps/unix/sysv/linux/statx_cp.c: trailing lines
240 lines
8.5 KiB
C
240 lines
8.5 KiB
C
/* Atomic operations. PowerPC64 version.
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Copyright (C) 2003-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/* POWER6 adds a "Mutex Hint" to the Load and Reserve instruction.
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This is a hint to the hardware to expect additional updates adjacent
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to the lock word or not. If we are acquiring a Mutex, the hint
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should be true. Otherwise we releasing a Mutex or doing a simple
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atomic operation. In that case we don't expect additional updates
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adjacent to the lock word after the Store Conditional and the hint
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should be false. */
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#if defined _ARCH_PWR6 || defined _ARCH_PWR6X
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# define MUTEX_HINT_ACQ ",1"
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# define MUTEX_HINT_REL ",0"
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#else
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# define MUTEX_HINT_ACQ
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# define MUTEX_HINT_REL
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#endif
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#define __HAVE_64B_ATOMICS 1
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#define USE_ATOMIC_COMPILER_BUILTINS 0
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#define ATOMIC_EXCHANGE_USES_CAS 1
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/* The 32-bit exchange_bool is different on powerpc64 because the subf
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does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
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(a load word and zero (high 32) form) load.
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In powerpc64 register values are 64-bit by default, including oldval.
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The value in old val unknown sign extension, lwarx loads the 32-bit
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value as unsigned. So we explicitly clear the high 32 bits in oldval. */
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#define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
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({ \
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unsigned int __tmp, __tmp2; \
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__asm __volatile (" clrldi %1,%1,32\n" \
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"1: lwarx %0,0,%2" MUTEX_HINT_ACQ "\n" \
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" subf. %0,%1,%0\n" \
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" bne 2f\n" \
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" stwcx. %4,0,%2\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp), "=r" (__tmp2) \
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: "b" (mem), "1" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp != 0; \
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})
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/*
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* Only powerpc64 processors support Load doubleword and reserve index (ldarx)
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* and Store doubleword conditional indexed (stdcx) instructions. So here
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* we define the 64-bit forms.
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*/
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#define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
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({ \
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unsigned long __tmp; \
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__asm __volatile ( \
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"1: ldarx %0,0,%1" MUTEX_HINT_ACQ "\n" \
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" subf. %0,%2,%0\n" \
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" bne 2f\n" \
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" stdcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp) \
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: "b" (mem), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp != 0; \
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})
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#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ \
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__typeof (*(mem)) __tmp; \
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__typeof (mem) __memp = (mem); \
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__asm __volatile ( \
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"1: ldarx %0,0,%1" MUTEX_HINT_ACQ "\n" \
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" cmpd %0,%2\n" \
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" bne 2f\n" \
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" stdcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp) \
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: "b" (__memp), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp; \
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})
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#define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \
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({ \
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__typeof (*(mem)) __tmp; \
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__typeof (mem) __memp = (mem); \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: ldarx %0,0,%1" MUTEX_HINT_REL "\n" \
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" cmpd %0,%2\n" \
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" bne 2f\n" \
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" stdcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " \
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: "=&r" (__tmp) \
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: "b" (__memp), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp; \
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})
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#define __arch_atomic_exchange_64_acq(mem, value) \
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({ \
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__typeof (*mem) __val; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: ldarx %0,0,%2" MUTEX_HINT_ACQ "\n" \
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" stdcx. %3,0,%2\n" \
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" bne- 1b\n" \
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" " __ARCH_ACQ_INSTR \
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: "=&r" (__val), "=m" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_exchange_64_rel(mem, value) \
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({ \
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__typeof (*mem) __val; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: ldarx %0,0,%2" MUTEX_HINT_REL "\n" \
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" stdcx. %3,0,%2\n" \
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" bne- 1b" \
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: "=&r" (__val), "=m" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_exchange_and_add_64(mem, value) \
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({ \
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__typeof (*mem) __val, __tmp; \
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__asm __volatile ("1: ldarx %0,0,%3\n" \
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" add %1,%0,%4\n" \
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" stdcx. %1,0,%3\n" \
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" bne- 1b" \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_exchange_and_add_64_acq(mem, value) \
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({ \
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__typeof (*mem) __val, __tmp; \
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__asm __volatile ("1: ldarx %0,0,%3" MUTEX_HINT_ACQ "\n" \
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" add %1,%0,%4\n" \
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" stdcx. %1,0,%3\n" \
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" bne- 1b\n" \
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__ARCH_ACQ_INSTR \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_exchange_and_add_64_rel(mem, value) \
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({ \
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__typeof (*mem) __val, __tmp; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: ldarx %0,0,%3" MUTEX_HINT_REL "\n" \
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" add %1,%0,%4\n" \
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" stdcx. %1,0,%3\n" \
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" bne- 1b" \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_increment_val_64(mem) \
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({ \
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__typeof (*(mem)) __val; \
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__asm __volatile ("1: ldarx %0,0,%2\n" \
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" addi %0,%0,1\n" \
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" stdcx. %0,0,%2\n" \
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" bne- 1b" \
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: "=&b" (__val), "=m" (*mem) \
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: "b" (mem), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_decrement_val_64(mem) \
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({ \
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__typeof (*(mem)) __val; \
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__asm __volatile ("1: ldarx %0,0,%2\n" \
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" subi %0,%0,1\n" \
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" stdcx. %0,0,%2\n" \
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" bne- 1b" \
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: "=&b" (__val), "=m" (*mem) \
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: "b" (mem), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_decrement_if_positive_64(mem) \
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({ int __val, __tmp; \
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__asm __volatile ("1: ldarx %0,0,%3\n" \
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" cmpdi 0,%0,0\n" \
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" addi %1,%0,-1\n" \
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" ble 2f\n" \
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" stdcx. %1,0,%3\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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/*
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* All powerpc64 processors support the new "light weight" sync (lwsync).
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*/
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#define atomic_read_barrier() __asm ("lwsync" ::: "memory")
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/*
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* "light weight" sync can also be used for the release barrier.
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*/
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#define __ARCH_REL_INSTR "lwsync"
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#define atomic_write_barrier() __asm ("lwsync" ::: "memory")
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/*
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* Include the rest of the atomic ops macros which are common to both
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* powerpc32 and powerpc64.
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*/
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#include_next <atomic-machine.h>
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