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2002-06-05 Brian Youmans <3diff@gnu.org> * sysdeps/ia64/fpu/e_acos.S: Added text of Intel license. * sysdeps/ia64/fpu/e_acosf.S: Likewise. * sysdeps/ia64/fpu/e_acosl.S: Likewise. * sysdeps/ia64/fpu/e_asin.S: Likewise. * sysdeps/ia64/fpu/e_asinf.S: Likewise. * sysdeps/ia64/fpu/e_asinl.S: Likewise. * sysdeps/ia64/fpu/e_atan2.S: Likewise. * sysdeps/ia64/fpu/e_atan2f.S: Likewise. * sysdeps/ia64/fpu/e_cosh.S: Likewise. * sysdeps/ia64/fpu/e_coshf.S: Likewise. * sysdeps/ia64/fpu/e_coshl.S: Likewise. * sysdeps/ia64/fpu/e_exp.S: Likewise. * sysdeps/ia64/fpu/e_expf.S: Likewise. * sysdeps/ia64/fpu/e_fmod.S: Likewise. * sysdeps/ia64/fpu/e_fmodf.S: Likewise. * sysdeps/ia64/fpu/e_fmodl.S: Likewise. * sysdeps/ia64/fpu/e_hypot.S: Likewise. * sysdeps/ia64/fpu/e_hypotf.S: Likewise. * sysdeps/ia64/fpu/e_hypotl.S: Likewise. * sysdeps/ia64/fpu/e_log.S: Likewise. * sysdeps/ia64/fpu/e_logf.S: Likewise. * sysdeps/ia64/fpu/e_pow.S: Likewise. * sysdeps/ia64/fpu/e_powf.S: Likewise. * sysdeps/ia64/fpu/e_powl.S: Likewise. * sysdeps/ia64/fpu/e_remainder.S: Likewise. * sysdeps/ia64/fpu/e_remainderf.S: Likewise. * sysdeps/ia64/fpu/e_remainderl.S: Likewise. * sysdeps/ia64/fpu/e_scalb.S: Likewise. * sysdeps/ia64/fpu/e_scalbf.S: Likewise. * sysdeps/ia64/fpu/e_scalbl.S: Likewise. * sysdeps/ia64/fpu/e_sinh.S: Likewise. * sysdeps/ia64/fpu/e_sinhf.S: Likewise. * sysdeps/ia64/fpu/e_sinhl.S: Likewise. * sysdeps/ia64/fpu/e_sqrt.S: Likewise. * sysdeps/ia64/fpu/e_sqrtf.S: Likewise. * sysdeps/ia64/fpu/e_sqrtl.S: Likewise. * sysdeps/ia64/fpu/libm_atan2_req.S: Likewise. * sysdeps/ia64/fpu/libm_error.c: Likewise. * sysdeps/ia64/fpu/libm_frexp4.S: Likewise. * sysdeps/ia64/fpu/libm_frexp4f.S: Likewise. * sysdeps/ia64/fpu/s_frexpl.c: Likewise. * sysdeps/ia64/fpu/s_ilogb.S: Likewise. * sysdeps/ia64/fpu/s_ilogbf.S: Likewise. * sysdeps/ia64/fpu/s_ilogbl.S: Likewise. * sysdeps/ia64/fpu/s_ldexp.S: Likewise. * sysdeps/ia64/fpu/s_ldexpf.S: Likewise. * sysdeps/ia64/fpu/s_ldexpl.S: Likewise. * sysdeps/ia64/fpu/s_log1p.S: Likewise. * sysdeps/ia64/fpu/s_log1pf.S: Likewise. * sysdeps/ia64/fpu/s_log1pl.S: Likewise. * sysdeps/ia64/fpu/s_logb.S: Likewise. * sysdeps/ia64/fpu/s_logbf.S: Likewise. * sysdeps/ia64/fpu/s_logbl.S: Likewise. * sysdeps/ia64/fpu/s_modf.S: Likewise. * sysdeps/ia64/fpu/s_modff.S: Likewise. * sysdeps/ia64/fpu/s_modfl.S: Likewise. * sysdeps/ia64/fpu/s_nearbyint.S: Likewise. * sysdeps/ia64/fpu/s_nearbyintf.S: Likewise. * sysdeps/ia64/fpu/s_nearbyintl.S: Likewise. * sysdeps/ia64/fpu/s_rint.S: Likewise. * sysdeps/ia64/fpu/s_rintf.S: Likewise. * sysdeps/ia64/fpu/s_rintl.S: Likewise. * sysdeps/ia64/fpu/s_round.S: Likewise. * sysdeps/ia64/fpu/s_roundf.S: Likewise. * sysdeps/ia64/fpu/s_roundl.S: Likewise. * sysdeps/ia64/fpu/s_scalbn.S: Likewise. * sysdeps/ia64/fpu/s_scalbnf.S: Likewise. * sysdeps/ia64/fpu/s_scalbnl.S: Likewise. * sysdeps/ia64/fpu/s_significand.S: Likewise. * sysdeps/ia64/fpu/s_significandf.S: Likewise. * sysdeps/ia64/fpu/s_significandl.S: Likewise. * sysdeps/ia64/fpu/s_tan.S: Likewise. * sysdeps/ia64/fpu/s_tanf.S: Likewise. * sysdeps/ia64/fpu/s_tanl.S: Likewise. * sysdeps/ia64/fpu/s_trunc.S: Likewise. * sysdeps/ia64/fpu/s_truncf.S: Likewise. * sysdeps/ia64/fpu/s_truncl.S: Likewise. * sysdeps/ieee754/dbl-64/doasin.c: Changed copyright notice to reflect IBM donation of math library to FSF * sysdeps/ieee754/dbl-64/dosincos.c: Likewise. * sysdeps/ieee754/dbl-64/e_asin.c: Likewise. * sysdeps/ieee754/dbl-64/e_atan2.c: Likewise. * sysdeps/ieee754/dbl-64/e_exp.c: Likewise. * sysdeps/ieee754/dbl-64/e_log.c: Likewise. * sysdeps/ieee754/dbl-64/e_pow.c: Likewise. * sysdeps/ieee754/dbl-64/e_remainder.c: Likewise. * sysdeps/ieee754/dbl-64/e_sqrt.c: Likewise. * sysdeps/ieee754/dbl-64/halfulp.c: Likewise. * sysdeps/ieee754/dbl-64/mpa.c: Likewise. * sysdeps/ieee754/dbl-64/mpatan.c: Likewise. * sysdeps/ieee754/dbl-64/mpatan2.c: Likewise. * sysdeps/ieee754/dbl-64/mpexp.c: Likewise. * sysdeps/ieee754/dbl-64/mplog.c: Likewise. * sysdeps/ieee754/dbl-64/mpsqrt.c: Likewise. * sysdeps/ieee754/dbl-64/mptan.c: Likewise. * sysdeps/ieee754/dbl-64/s_atan.c: Likewise. * sysdeps/ieee754/dbl-64/s_sin.c: Likewise. * sysdeps/ieee754/dbl-64/s_tan.c: Likewise. * sysdeps/ieee754/dbl-64/sincos32.c: Likewise. * sysdeps/ieee754/dbl-64/slowexp.c: Likewise. * sysdeps/ieee754/dbl-64/slowpow.c: Likewise. * sysdeps/gnu/netinet/udp.h: Added BSD copying permission notice * sysdeps/vax/__longjmp.c: Likewise. * sysdeps/vax/setjmp.c: Likewise. * libio/filedoalloc.c: Fixed BSD copying permission notice to remove advertising clause * sysdeps/vax/htonl.s: Likewise. * sysdeps/vax/htons.s: Likewise. * libio/wfiledoalloc.c: Likewise. * stdlib/random.c: Likewise. * stdlib/random_r.c: Likewise. * sysdeps/mach/sys/reboot.h: Likewise. * inet/getnameinfo.c: Deleted advertising clause from Inner Net License * sysdeps/posix/getaddrinfo.c: Likewise. * sunrpc/des_impl.c: Updated license permission notice to Lesser GPL and corrected pointer to point to the correct license.
898 lines
25 KiB
ArmAsm
898 lines
25 KiB
ArmAsm
.file "asin.s"
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// Copyright (C) 2000, 2001, Intel Corporation
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// All rights reserved.
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//
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// Contributed 2/2/2000 by John Harrison, Ted Kubaska, Bob Norin, Shane Story,
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// and Ping Tak Peter Tang of the Computational Software Lab, Intel Corporation.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// * The name of Intel Corporation may not be used to endorse or promote
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// products derived from this software without specific prior written
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// permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Intel Corporation is the author of this code, and requests that all
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// problem reports or change requests be submitted to it directly at
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// http://developer.intel.com/opensource.
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// History
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//==============================================================
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// 2/02/00 Initial version
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// 8/17/00 New and much faster algorithm.
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// 8/31/00 Avoided bank conflicts on loads, shortened |x|=1 path,
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// fixed mfb split issue stalls.
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// 12/19/00 Fixed small arg cases to force inexact, or inexact and underflow.
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// Description
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//=========================================
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// The asin function computes the principle value of the arc sine of x.
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// asin(0) returns 0, asin(1) returns pi/2, asin(-1) returns -pi/2.
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// A doman error occurs for arguments not in the range [-1,+1].
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// The asin function returns the arc sine in the range [-pi/2, +pi/2] radians.
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#include "libm_support.h"
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//
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// Assembly macros
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//=========================================
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// predicate registers
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//asin_pred_LEsqrt2by2 = p7
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//asin_pred_GTsqrt2by2 = p8
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// integer registers
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ASIN_Addr1 = r33
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ASIN_Addr2 = r34
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ASIN_FFFE = r35
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ASIN_lnorm_sig = r36
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ASIN_snorm_exp = r37
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GR_SAVE_B0 = r36
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GR_SAVE_PFS = r37
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GR_SAVE_GP = r38
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GR_Parameter_X = r39
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GR_Parameter_Y = r40
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GR_Parameter_RESULT = r41
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GR_Parameter_Tag = r42
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// floating point registers
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asin_coeff_P1 = f32
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asin_coeff_P2 = f33
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asin_coeff_P3 = f34
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asin_coeff_P4 = f35
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asin_coeff_P5 = f36
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asin_coeff_P6 = f37
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asin_coeff_P7 = f38
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asin_coeff_P8 = f39
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asin_coeff_P9 = f40
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asin_coeff_P10 = f41
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asin_coeff_P11 = f42
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asin_coeff_P12 = f43
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asin_coeff_P13 = f44
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asin_coeff_P14 = f45
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asin_coeff_P15 = f46
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asin_coeff_P16 = f47
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asin_coeff_P17 = f48
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asin_coeff_P18 = f49
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asin_coeff_P19 = f50
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asin_coeff_P20 = f51
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asin_coeff_P21 = f52
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asin_const_sqrt2by2 = f53
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asin_const_piby2 = f54
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asin_abs_x = f55
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asin_tx = f56
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asin_tx2 = f57
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asin_tx3 = f58
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asin_tx4 = f59
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asin_tx8 = f60
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asin_tx11 = f61
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asin_1poly_p8 = f62
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asin_1poly_p19 = f63
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asin_1poly_p4 = f64
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asin_1poly_p15 = f65
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asin_1poly_p6 = f66
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asin_1poly_p17 = f67
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asin_1poly_p0 = f68
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asin_1poly_p11 = f69
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asin_1poly_p2 = f70
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asin_1poly_p13 = f71
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asin_series_tx = f72
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asin_t = f73
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asin_t2 = f74
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asin_t3 = f75
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asin_t4 = f76
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asin_t8 = f77
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asin_t11 = f78
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asin_poly_p8 = f79
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asin_poly_p19 = f80
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asin_poly_p4 = f81
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asin_poly_p15 = f82
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asin_poly_p6 = f83
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asin_poly_p17 = f84
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asin_poly_p0 = f85
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asin_poly_p11 = f86
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asin_poly_p2 = f87
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asin_poly_p13 = f88
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asin_series_t = f89
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asin_1by2 = f90
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asin_3by2 = f91
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asin_5by2 = f92
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asin_11by4 = f93
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asin_35by8 = f94
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asin_63by8 = f95
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asin_231by16 = f96
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asin_y0 = f97
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asin_H0 = f98
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asin_S0 = f99
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asin_d = f100
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asin_l1 = f101
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asin_d2 = f102
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asin_T0 = f103
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asin_d1 = f104
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asin_e0 = f105
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asin_l2 = f106
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asin_d3 = f107
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asin_T3 = f108
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asin_S1 = f109
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asin_e1 = f110
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asin_z = f111
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answer2 = f112
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asin_sgn_x = f113
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asin_429by16 = f114
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asin_18by4 = f115
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asin_3by4 = f116
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asin_l3 = f117
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asin_T6 = f118
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asin_eps_exp = f119
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asin_eps_sig = f120
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asin_eps = f120
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// Data tables
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//==============================================================
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#ifdef _LIBC
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.rodata
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#else
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.data
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#endif
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.align 16
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asin_coeff_1_table:
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ASM_TYPE_DIRECTIVE(asin_coeff_1_table,@object)
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data8 0xE4E7E0A423A21249 , 0x00003FF8 //P7
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data8 0xC2F7EE0200FCE2A5 , 0x0000C003 //P18
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data8 0xB745D7F6C65C20E0 , 0x00003FF9 //P5
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data8 0xF75E381A323D4D94 , 0x0000C002 //P16
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data8 0x8959C2629C1024C0 , 0x0000C002 //P20
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data8 0xAFF68E7D241292C5 , 0x00003FF8 //P9
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data8 0xB6DB6DB7260AC30D , 0x00003FFA //P3
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data8 0xD0417CE2B41CB7BF , 0x0000C000 //P14
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data8 0x81D570FEA724E3E4 , 0x0000BFFD //P12
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data8 0xAAAAAAAAAAAAC277 , 0x00003FFC //P1
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data8 0xF534912FF3E7B76F , 0x00003FFF //P21
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data8 0xc90fdaa22168c235 , 0x00003fff // pi/2
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data8 0x0000000000000000 , 0x00000000 // pad to avoid data bank conflict
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ASM_SIZE_DIRECTIVE(asin_coeff_1_table)
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asin_coeff_2_table:
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ASM_TYPE_DIRECTIVE(asin_coeff_2_table,@object)
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data8 0x8E26AF5F29B39A2A , 0x00003FF9 //P6
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data8 0xB4F118A4B1015470 , 0x00004003 //P17
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data8 0xF8E38E10C25990E0 , 0x00003FF9 //P4
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data8 0x80F50489AEF1CAC6 , 0x00004002 //P15
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data8 0x92728015172CFE1C , 0x00004003 //P19
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data8 0xBBC3D831D4595971 , 0x00003FF8 //P8
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data8 0x999999999952A5C3 , 0x00003FFB //P2
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data8 0x855576BE6F0975EC , 0x00003FFF //P13
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data8 0xF12420E778077D89 , 0x00003FFA //P11
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data8 0xB6590FF4D23DE003 , 0x00003FF3 //P10
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data8 0xb504f333f9de6484 , 0x00003ffe // sqrt(2)/2
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ASM_SIZE_DIRECTIVE(asin_coeff_2_table)
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.align 32
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.global asin
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.section .text
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.proc asin
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.align 32
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asin:
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{ .mfi
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alloc r32 = ar.pfs,1,6,4,0
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fma.s1 asin_tx = f8,f8,f0
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addl ASIN_Addr2 = @ltoff(asin_coeff_2_table),gp
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}
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{ .mfi
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mov ASIN_FFFE = 0xFFFE
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fnma.s1 asin_t = f8,f8,f1
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addl ASIN_Addr1 = @ltoff(asin_coeff_1_table),gp
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}
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;;
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{ .mfi
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setf.exp asin_1by2 = ASIN_FFFE
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fmerge.s asin_abs_x = f1,f8
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nop.i 999 ;;
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}
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{ .mmf
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ld8 ASIN_Addr1 = [ASIN_Addr1]
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ld8 ASIN_Addr2 = [ASIN_Addr2]
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fmerge.s asin_sgn_x = f8,f1 ;;
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}
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{ .mfi
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ldfe asin_coeff_P7 = [ASIN_Addr1],16
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fma.s1 asin_tx2 = asin_tx,asin_tx,f0
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nop.i 999
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}
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{ .mfi
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ldfe asin_coeff_P6 = [ASIN_Addr2],16
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fma.s1 asin_t2 = asin_t,asin_t,f0
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nop.i 999;;
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}
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{ .mmf
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ldfe asin_coeff_P18 = [ASIN_Addr1],16
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ldfe asin_coeff_P17 = [ASIN_Addr2],16
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fclass.m.unc p8,p0 = f8, 0xc3 //@qnan |@snan
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}
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;;
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{ .mmf
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ldfe asin_coeff_P5 = [ASIN_Addr1],16
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ldfe asin_coeff_P4 = [ASIN_Addr2],16
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frsqrta.s1 asin_y0,p0 = asin_t
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}
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;;
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{ .mfi
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ldfe asin_coeff_P16 = [ASIN_Addr1],16
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fcmp.gt.s1 p9,p0 = asin_abs_x,f1
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nop.i 999
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}
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{ .mfb
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ldfe asin_coeff_P15 = [ASIN_Addr2],16
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(p8) fma.d f8 = f8,f1,f0
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(p8) br.ret.spnt b0
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}
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;;
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{ .mmf
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ldfe asin_coeff_P20 = [ASIN_Addr1],16
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ldfe asin_coeff_P19 = [ASIN_Addr2],16
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fclass.m.unc p8,p0 = f8, 0x07 //@zero
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}
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;;
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{ .mfi
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ldfe asin_coeff_P9 = [ASIN_Addr1],16
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fma.s1 asin_t4 = asin_t2,asin_t2,f0
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(p9) mov GR_Parameter_Tag = 61
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}
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{ .mfi
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ldfe asin_coeff_P8 = [ASIN_Addr2],16
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fma.s1 asin_3by2 = asin_1by2,f1,f1
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nop.i 999;;
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}
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{ .mfi
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ldfe asin_coeff_P2 = [ASIN_Addr2],16
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fma.s1 asin_tx4 = asin_tx2,asin_tx2,f0
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nop.i 999
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}
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{ .mfb
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ldfe asin_coeff_P3 = [ASIN_Addr1],16
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fma.s1 asin_t3 = asin_t,asin_t2,f0
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(p8) br.ret.spnt b0
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}
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;;
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{ .mfi
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ldfe asin_coeff_P13 = [ASIN_Addr2],16
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fma.s1 asin_H0 = asin_y0,asin_1by2,f0
|
|
nop.i 999
|
|
}
|
|
{ .mfb
|
|
ldfe asin_coeff_P14 = [ASIN_Addr1],16
|
|
fma.s1 asin_S0 = asin_y0,asin_t,f0
|
|
(p9) br.cond.spnt __libm_error_region
|
|
}
|
|
;;
|
|
|
|
|
|
{ .mfi
|
|
ldfe asin_coeff_P11 = [ASIN_Addr2],16
|
|
fcmp.eq.s1 p6,p0 = asin_abs_x,f1
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
ldfe asin_coeff_P12 = [ASIN_Addr1],16
|
|
fma.s1 asin_tx3 = asin_tx,asin_tx2,f0
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
ldfe asin_coeff_P10 = [ASIN_Addr2],16
|
|
fma.s1 asin_1poly_p6 = asin_tx,asin_coeff_P7,asin_coeff_P6
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
ldfe asin_coeff_P1 = [ASIN_Addr1],16
|
|
fma.s1 asin_poly_p6 = asin_t,asin_coeff_P7,asin_coeff_P6
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
ldfe asin_const_sqrt2by2 = [ASIN_Addr2],16
|
|
fma.s1 asin_5by2 = asin_3by2,f1,f1
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
ldfe asin_coeff_P21 = [ASIN_Addr1],16
|
|
fma.s1 asin_11by4 = asin_3by2,asin_3by2,asin_1by2
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
ldfe asin_const_piby2 = [ASIN_Addr1],16
|
|
fma.s1 asin_poly_p17 = asin_t,asin_coeff_P18,asin_coeff_P17
|
|
nop.i 999
|
|
}
|
|
{ .mfb
|
|
nop.m 999
|
|
fma.s1 asin_3by4 = asin_3by2,asin_1by2,f0
|
|
(p6) br.cond.spnt L(ASIN_ABS_1) // Branch to short exit if |x|=1
|
|
}
|
|
;;
|
|
|
|
|
|
{ .mfi
|
|
addl ASIN_lnorm_sig = -0x1,r0 // Form significand 0xffffffffffffffff
|
|
fma.s1 asin_poly_p15 = asin_t,asin_coeff_P16,asin_coeff_P15
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
addl ASIN_snorm_exp = 0x0c001,r0 // Form small exponent
|
|
fnma.s1 asin_d = asin_S0,asin_H0,asin_1by2
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
// Form the exponent and significand of a small number
|
|
{ .mfi
|
|
setf.sig asin_eps_sig = ASIN_lnorm_sig
|
|
fma.s1 asin_poly_p19 = asin_t,asin_coeff_P20,asin_coeff_P19
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
setf.exp asin_eps_exp = ASIN_snorm_exp
|
|
fma.s1 asin_poly_p4 = asin_t,asin_coeff_P5,asin_coeff_P4
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p17 = asin_tx,asin_coeff_P18,asin_coeff_P17
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p8 = asin_t,asin_coeff_P9,asin_coeff_P8
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fms.s1 asin_35by8 = asin_5by2,asin_11by4,asin_5by2
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_63by8 = asin_5by2,asin_11by4,f1
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p13 = asin_t,asin_coeff_P14,asin_coeff_P13
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_18by4 = asin_3by2,asin_5by2,asin_3by4
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_l1 = asin_5by2,asin_d,asin_3by2
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_d2 = asin_d,asin_d,f0
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p15 = asin_t2,asin_poly_p17,asin_poly_p15
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_T0 = asin_d,asin_S0,f0
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p19 = asin_t2,asin_coeff_P21,asin_poly_p19
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p4 = asin_t2,asin_poly_p6,asin_poly_p4
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_d1 = asin_35by8,asin_d,f0
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_231by16 = asin_3by2,asin_35by8,asin_63by8
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p2 = asin_t,asin_coeff_P3,asin_coeff_P2
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p8 = asin_t2,asin_coeff_P10,asin_poly_p8
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p11 = asin_t,asin_coeff_P12,asin_coeff_P11
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_e0 = asin_d2,asin_l1,asin_d
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p15 = asin_tx,asin_coeff_P16,asin_coeff_P15
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p0 = asin_t,asin_coeff_P1,f1
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p19 = asin_tx,asin_coeff_P20,asin_coeff_P19
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p4 = asin_tx,asin_coeff_P5,asin_coeff_P4
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p8 = asin_tx,asin_coeff_P9,asin_coeff_P8
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_l2 = asin_231by16,asin_d,asin_63by8
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_d3 = asin_d2,asin_d,f0
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_T3 = asin_d2,asin_T0,f0
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_429by16 = asin_18by4,asin_11by4,asin_231by16
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_S1 = asin_e0,asin_S0,asin_S0
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p4 = asin_t4,asin_poly_p8,asin_poly_p4
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p15 = asin_t4,asin_poly_p19,asin_poly_p15
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p0 = asin_t2,asin_poly_p2,asin_poly_p0
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p11 = asin_t2,asin_poly_p13,asin_poly_p11
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_t8 = asin_t4,asin_t4,f0
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_e1 = asin_d2,asin_l2,asin_d1
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p4 = asin_tx2,asin_1poly_p6,asin_1poly_p4
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p15 = asin_tx2,asin_1poly_p17,asin_1poly_p15
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p8 = asin_tx2,asin_coeff_P10,asin_1poly_p8
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p19 = asin_tx2,asin_coeff_P21,asin_1poly_p19
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p2 = asin_tx,asin_coeff_P3,asin_coeff_P2
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p13 = asin_tx,asin_coeff_P14,asin_coeff_P13
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p0 = asin_tx,asin_coeff_P1,f1
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p11 = asin_tx,asin_coeff_P12,asin_coeff_P11
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_l3 = asin_429by16,asin_d,f0
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_z = asin_e1,asin_T3,asin_S1
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p11 = asin_t4,asin_poly_p15,asin_poly_p11
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_T6 = asin_T3,asin_d3,f0
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_t11 = asin_t8,asin_t3,f0
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_poly_p0 = asin_t4,asin_poly_p4,asin_poly_p0
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p4 = asin_tx4,asin_1poly_p8,asin_1poly_p4
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p15 = asin_tx4,asin_1poly_p19,asin_1poly_p15
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p0 = asin_tx2,asin_1poly_p2,asin_1poly_p0
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p11 = asin_tx2,asin_1poly_p13,asin_1poly_p11
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
// fcmp.le.s1 asin_pred_LEsqrt2by2,asin_pred_GTsqrt2by2 = asin_abs_x,asin_const_sqrt2by2
|
|
fcmp.le.s1 p7,p8 = asin_abs_x,asin_const_sqrt2by2
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_tx8 = asin_tx4,asin_tx4,f0
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
// Form a small number to force inexact flag for small args
|
|
{ .mfi
|
|
nop.m 999
|
|
fmerge.se asin_eps = asin_eps_exp,asin_eps_sig
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_z = asin_l3,asin_T6,asin_z
|
|
nop.i 999;;
|
|
}
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_series_t = asin_t11,asin_poly_p11,asin_poly_p0
|
|
nop.i 999;;
|
|
}
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p0 = asin_tx4,asin_1poly_p4,asin_1poly_p0
|
|
nop.i 999
|
|
}
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_1poly_p11 = asin_tx4,asin_1poly_p15,asin_1poly_p11
|
|
nop.i 999;;
|
|
}
|
|
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_tx11 = asin_tx8,asin_tx3,f0
|
|
nop.i 999;;
|
|
}
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
//(asin_pred_GTsqrt2by2) fnma.s1 answer2 = asin_z,asin_series_t,asin_const_piby2
|
|
(p8) fnma.s1 answer2 = asin_z,asin_series_t,asin_const_piby2
|
|
nop.i 999;;
|
|
}
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
fma.s1 asin_series_tx = asin_tx11,asin_1poly_p11,asin_1poly_p0
|
|
nop.i 999;;
|
|
}
|
|
|
|
{ .mfi
|
|
nop.m 999
|
|
//(asin_pred_GTsqrt2by2) fma.d f8 = asin_sgn_x,answer2,f0
|
|
(p8) fma.d f8 = asin_sgn_x,answer2,f0
|
|
nop.i 999;;
|
|
}
|
|
|
|
// asin_eps is added only to force inexact and possibly underflow flag
|
|
// in case asin_series_tx is zero
|
|
//
|
|
{ .mfi
|
|
nop.m 999
|
|
(p7) fma.d asin_eps = f8,asin_series_tx,asin_eps
|
|
nop.i 999
|
|
}
|
|
{ .mfb
|
|
nop.m 999
|
|
//(asin_pred_LEsqrt2by2) fma.d f8 = f8,asin_series_tx,f0
|
|
(p7) fma.d f8 = f8,asin_series_tx,f0
|
|
br.ret.sptk b0
|
|
}
|
|
;;
|
|
|
|
|
|
L(ASIN_ABS_1):
|
|
// Here for short exit if |x|=1
|
|
{ .mfb
|
|
nop.m 999
|
|
fma.d f8 = asin_sgn_x,asin_const_piby2,f0
|
|
br.ret.sptk b0
|
|
}
|
|
;;
|
|
|
|
|
|
.endp asin
|
|
ASM_SIZE_DIRECTIVE(asin)
|
|
|
|
.proc __libm_error_region
|
|
__libm_error_region:
|
|
.prologue
|
|
{ .mfi
|
|
add GR_Parameter_Y=-32,sp // Parameter 2 value
|
|
nop.f 999
|
|
.save ar.pfs,GR_SAVE_PFS
|
|
mov GR_SAVE_PFS=ar.pfs // Save ar.pfs
|
|
}
|
|
{ .mfi
|
|
.fframe 64
|
|
add sp=-64,sp // Create new stack
|
|
nop.f 0
|
|
mov GR_SAVE_GP=gp // Save gp
|
|
};;
|
|
{ .mmi
|
|
stfs [GR_Parameter_Y] = f1,16 // Store Parameter 2 on stack
|
|
add GR_Parameter_X = 16,sp // Parameter 1 address
|
|
.save b0, GR_SAVE_B0
|
|
mov GR_SAVE_B0=b0 // Save b0
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};;
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|
|
|
.body
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frcpa.s0 f9,p0 = f0,f0
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|
;;
|
|
|
|
{ .mib
|
|
stfd [GR_Parameter_X] = f8 // Store Parameter 1 on stack
|
|
add GR_Parameter_RESULT = 0,GR_Parameter_Y
|
|
nop.b 0 // Parameter 3 address
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|
}
|
|
{ .mib
|
|
stfd [GR_Parameter_Y] = f9,-16 // Store Parameter 3 on stack
|
|
adds r32 = 48,sp
|
|
br.call.sptk b0=__libm_error_support# // Call error handling function
|
|
};;
|
|
{ .mmi
|
|
ldfd f8 = [r32] // Get return result off stack
|
|
.restore sp
|
|
add sp = 64,sp // Restore stack pointer
|
|
mov b0 = GR_SAVE_B0 // Restore return address
|
|
};;
|
|
{ .mib
|
|
mov gp = GR_SAVE_GP // Restore gp
|
|
mov ar.pfs = GR_SAVE_PFS // Restore ar.pfs
|
|
br.ret.sptk b0 // Return
|
|
|
|
};;
|
|
|
|
.endp __libm_error_region
|
|
ASM_SIZE_DIRECTIVE(__libm_error_region)
|
|
|
|
.type __libm_error_support,@function
|
|
.global __libm_error_support
|