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I used these shell commands: ../glibc/scripts/update-copyrights $PWD/../gnulib/build-aux/update-copyright (cd ../glibc && git commit -am"[this commit message]") and then ignored the output, which consisted lines saying "FOO: warning: copyright statement not found" for each of 6694 files FOO. I then removed trailing white space from benchtests/bench-pthread-locks.c and iconvdata/tst-iconv-big5-hkscs-to-2ucs4.c, to work around this diagnostic from Savannah: remote: *** pre-commit check failed ... remote: *** error: lines with trailing whitespace found remote: error: hook declined to update refs/heads/master
188 lines
5.1 KiB
ArmAsm
188 lines
5.1 KiB
ArmAsm
/* Optimized strspn implementation for Power8.
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Copyright (C) 2016-2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/* size_t [r3] strspn (const char *string [r3],
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const char *needleAccept [r4]) */
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/* This takes a novel approach by computing a 256 bit mask whereby
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each set bit implies the byte is "accepted". P8 vector hardware
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has extremely efficient hardware for selecting bits from a mask.
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One might ask "why not use bpermd for short strings"? It is
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so slow that its performance about matches the generic PPC64
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variant without any fancy masking, with the added expense of
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making the mask. That was the first variant of this. */
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#include "sysdep.h"
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#ifndef USE_AS_STRCSPN
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# define USE_AS_STRCSPN 0
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# ifndef STRSPN
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# define STRSPN strspn
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# endif
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# define INITIAL_MASK 0
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# define UPDATE_MASK(RA, RS, RB) or RA, RS, RB
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#else
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# ifndef STRSPN
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# define STRSPN strcspn
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# endif
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# define INITIAL_MASK -1
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# define UPDATE_MASK(RA, RS, RB) andc RA, RS, RB
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#endif
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/* Simple macro to use VSX instructions in overlapping VR's. */
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#define XXVR(insn, vrt, vra, vrb) \
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insn 32+vrt, 32+vra, 32+vrb
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.machine power8
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ENTRY_TOCLESS (STRSPN, 4)
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CALL_MCOUNT 2
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/* Generate useful constants for later on. */
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vspltisb v1, 7
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vspltisb v2, -1
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vslb v1, v1, v1 /* 0x80 to swap high bit for vbpermq. */
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vspltisb v10, 0
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vsldoi v4, v10, v2, 2 /* 0xFFFF into vr4. */
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XXVR(xxmrgld, v4, v4, v10) /* Mask for checking matches. */
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/* Prepare to compute 256b mask. */
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addi r4, r4, -1
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li r5, INITIAL_MASK
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li r6, INITIAL_MASK
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li r7, INITIAL_MASK
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li r8, INITIAL_MASK
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#if USE_AS_STRCSPN
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/* Ensure the null character never matches by clearing ISA bit 0 in
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in r5 which is the bit which will check for it in the later usage
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of vbpermq. */
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srdi r5, r5, 1
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#endif
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li r11, 1
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sldi r11, r11, 63
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/* Start interleaved Mask computation.
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This will eventually or 1's into ignored bits from vbpermq. */
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lvsr v11, 0, r3
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vspltb v11, v11, 0 /* Splat shift constant. */
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/* Build a 256b mask in r5-r8. */
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.align 4
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L(next_needle):
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lbzu r9, 1(r4)
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cmpldi cr0, r9, 0
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cmpldi cr1, r9, 128
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/* This is a little tricky. srd only uses the first 7 bits,
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and if bit 7 is set, value is always 0. So, we can
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effectively shift 128b in this case. */
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xori r12, r9, 0x40 /* Invert bit 6. */
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srd r10, r11, r9 /* Mask for bits 0-63. */
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srd r12, r11, r12 /* Mask for bits 64-127. */
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beq cr0, L(start_cmp)
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/* Now, or the value into the correct GPR. */
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bge cr1,L(needle_gt128)
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UPDATE_MASK (r5, r5, r10) /* 0 - 63. */
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UPDATE_MASK (r6, r6, r12) /* 64 - 127. */
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b L(next_needle)
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.align 4
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L(needle_gt128):
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UPDATE_MASK (r7, r7, r10) /* 128 - 191. */
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UPDATE_MASK (r8, r8, r12) /* 192 - 255. */
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b L(next_needle)
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.align 4
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L(start_cmp):
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/* Move and merge bitmap into 2 VRs. bpermd is slower on P8. */
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mr r0, r3 /* Save r3 for final length computation. */
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mtvrd v5, r5
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mtvrd v6, r6
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mtvrd v7, r7
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mtvrd v8, r8
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/* Continue interleaved mask generation. */
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#ifdef __LITTLE_ENDIAN__
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vsrw v11, v2, v11 /* Note, shift ignores higher order bits. */
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vsplth v11, v11, 0 /* Only care about the high 16 bits of v10. */
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#else
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vslw v11, v2, v11 /* Note, shift ignores higher order bits. */
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vsplth v11, v11, 1 /* Only care about the low 16 bits of v10. */
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#endif
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lvx v0, 0, r3 /* Note, unaligned load ignores lower bits. */
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/* Do the merging of the bitmask. */
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XXVR(xxmrghd, v5, v5, v6)
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XXVR(xxmrghd, v6, v7, v8)
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/* Finish mask generation. */
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vand v11, v11, v4 /* Throwaway bits not in the mask. */
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/* Compare the first 1-16B, while masking unwanted bytes. */
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clrrdi r3, r3, 4 /* Note, counts from qw boundaries. */
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vxor v9, v0, v1 /* Swap high bit. */
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vbpermq v8, v5, v0
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vbpermq v7, v6, v9
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vor v7, v7, v8
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vor v7, v7, v11 /* Ignore non-participating bytes. */
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vcmpequh. v8, v7, v4
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bnl cr6, L(done)
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addi r3, r3, 16
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.align 4
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L(vec):
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lvx v0, 0, r3
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addi r3, r3, 16
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vxor v9, v0, v1 /* Swap high bit. */
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vbpermq v8, v5, v0
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vbpermq v7, v6, v9
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vor v7, v7, v8
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vcmpequh. v8, v7, v4
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blt cr6, L(vec)
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addi r3, r3, -16
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L(done):
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subf r3, r0, r3
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mfvrd r10, v7
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#ifdef __LITTLE_ENDIAN__
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addi r0, r10, 1 /* Count the trailing 1's. */
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andc r10, r10, r0
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popcntd r10, r10
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#else
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xori r10, r10, 0xffff /* Count leading 1's by inverting. */
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addi r3, r3, -48 /* Account for the extra leading zeros. */
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cntlzd r10, r10
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#endif
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add r3, r3, r10
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blr
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END(STRSPN)
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libc_hidden_builtin_def (STRSPN)
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