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c9a8c526ac
Here is implementation of vectorized sincos containing SSE, AVX, AVX2 and AVX512 versions according to Vector ABI <https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>. * NEWS: Mention addition of x86_64 vector sincos. * bits/libm-simd-decl-stubs.h: Added stubs for sincos. * math/math.h (__MATHDECL_VEC): New macro. * math/bits/mathcalls.h: Added sincos declaration with __MATHDECL_VEC. * math/gen-libm-have-vector-test.sh: Added generation of sincos wrapper declaration under condition. * math/test-vec-loop.h (TEST_VEC_LOOP): Refactored. * math/test-double-vlen2.h: Added wrapper for sincos tests, reflected TEST_VEC_LOOP change. * math/test-double-vlen4.h: Likewise. * math/test-double-vlen8.h: Likewise. * math/test-float-vlen16.h: Reflected TEST_VEC_LOOP change. * math/test-float-vlen4.h: Likewise. * math/test-float-vlen8.h: Likewise. * sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New symbols added. * sysdeps/x86/fpu/bits/math-vector.h: Added sincos SIMD declaration. * sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files. * sysdeps/x86_64/fpu/Versions: New versions added. * sysdeps/x86_64/fpu/libm-test-ulps: Regenerated. * sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added build of SSE, AVX2 and AVX512 IFUNC versions. * sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core_sse4.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core_avx2.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.S: New file. * sysdeps/x86_64/fpu/svml_d_sincos2_core.S: New file. * sysdeps/x86_64/fpu/svml_d_sincos4_core.S: New file. * sysdeps/x86_64/fpu/svml_d_sincos4_core_avx.S: New file. * sysdeps/x86_64/fpu/svml_d_sincos8_core.S: New file. * sysdeps/x86_64/fpu/svml_d_sincos_data.S: New file. * sysdeps/x86_64/fpu/svml_d_sincos_data.h: New file. * sysdeps/x86_64/fpu/svml_d_wrapper_impl.h: Added wrappers for sincos. * sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c: Vector sincos tests. * sysdeps/x86_64/fpu/test-double-vlen2.c: Likewise. * sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c: Likewise. * sysdeps/x86_64/fpu/test-double-vlen4-avx2.c: Likewise. * sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c: Likewise. * sysdeps/x86_64/fpu/test-double-vlen4.c: Likewise. * sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: Likewise. * sysdeps/x86_64/fpu/test-double-vlen8.c: Likewise.
382 lines
11 KiB
C
382 lines
11 KiB
C
/* Wrapper implementations of vector math functions.
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Copyright (C) 2014-2015 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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/* SSE2 ISA version as wrapper to scalar. */
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.macro WRAPPER_IMPL_SSE2 callee
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subq $40, %rsp
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cfi_adjust_cfa_offset(40)
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movaps %xmm0, (%rsp)
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call \callee@PLT
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movsd %xmm0, 16(%rsp)
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movsd 8(%rsp), %xmm0
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call \callee@PLT
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movsd 16(%rsp), %xmm1
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movsd %xmm0, 24(%rsp)
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unpcklpd %xmm0, %xmm1
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movaps %xmm1, %xmm0
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addq $40, %rsp
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cfi_adjust_cfa_offset(-40)
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ret
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.endm
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/* 2 argument SSE2 ISA version as wrapper to scalar. */
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.macro WRAPPER_IMPL_SSE2_ff callee
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subq $56, %rsp
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cfi_adjust_cfa_offset(56)
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movaps %xmm0, (%rsp)
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movaps %xmm1, 16(%rsp)
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call \callee@PLT
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movsd %xmm0, 32(%rsp)
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movsd 8(%rsp), %xmm0
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movsd 24(%rsp), %xmm1
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call \callee@PLT
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movsd 32(%rsp), %xmm1
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movsd %xmm0, 40(%rsp)
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unpcklpd %xmm0, %xmm1
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movaps %xmm1, %xmm0
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addq $56, %rsp
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cfi_adjust_cfa_offset(-56)
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ret
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.endm
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/* 3 argument SSE2 ISA version as wrapper to scalar. */
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.macro WRAPPER_IMPL_SSE2_fFF callee
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pushq %rbp
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cfi_adjust_cfa_offset (8)
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cfi_rel_offset (%rbp, 0)
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pushq %rbx
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cfi_adjust_cfa_offset (8)
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cfi_rel_offset (%rbx, 0)
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movq %rdi, %rbp
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movq %rsi, %rbx
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subq $40, %rsp
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cfi_adjust_cfa_offset(40)
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leaq 16(%rsp), %rsi
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leaq 24(%rsp), %rdi
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movaps %xmm0, (%rsp)
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call \callee@PLT
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leaq 16(%rsp), %rsi
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leaq 24(%rsp), %rdi
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movsd 24(%rsp), %xmm0
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movapd (%rsp), %xmm1
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movsd %xmm0, 0(%rbp)
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unpckhpd %xmm1, %xmm1
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movsd 16(%rsp), %xmm0
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movsd %xmm0, (%rbx)
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movapd %xmm1, %xmm0
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call \callee@PLT
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movsd 24(%rsp), %xmm0
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movsd %xmm0, 8(%rbp)
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movsd 16(%rsp), %xmm0
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movsd %xmm0, 8(%rbx)
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addq $40, %rsp
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cfi_adjust_cfa_offset(-40)
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popq %rbx
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cfi_adjust_cfa_offset (-8)
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cfi_restore (%rbx)
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popq %rbp
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cfi_adjust_cfa_offset (-8)
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cfi_restore (%rbp)
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ret
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.endm
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/* AVX/AVX2 ISA version as wrapper to SSE ISA version. */
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.macro WRAPPER_IMPL_AVX callee
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pushq %rbp
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cfi_adjust_cfa_offset (8)
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cfi_rel_offset (%rbp, 0)
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movq %rsp, %rbp
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cfi_def_cfa_register (%rbp)
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andq $-32, %rsp
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subq $32, %rsp
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vextractf128 $1, %ymm0, (%rsp)
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vzeroupper
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call HIDDEN_JUMPTARGET(\callee)
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vmovapd %xmm0, 16(%rsp)
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vmovaps (%rsp), %xmm0
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call HIDDEN_JUMPTARGET(\callee)
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vmovapd %xmm0, %xmm1
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vmovapd 16(%rsp), %xmm0
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vinsertf128 $1, %xmm1, %ymm0, %ymm0
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movq %rbp, %rsp
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cfi_def_cfa_register (%rsp)
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popq %rbp
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cfi_adjust_cfa_offset (-8)
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cfi_restore (%rbp)
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ret
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.endm
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/* 2 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */
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.macro WRAPPER_IMPL_AVX_ff callee
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pushq %rbp
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cfi_adjust_cfa_offset (8)
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cfi_rel_offset (%rbp, 0)
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movq %rsp, %rbp
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cfi_def_cfa_register (%rbp)
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andq $-32, %rsp
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subq $64, %rsp
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vextractf128 $1, %ymm0, 16(%rsp)
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vextractf128 $1, %ymm1, (%rsp)
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vzeroupper
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call HIDDEN_JUMPTARGET(\callee)
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vmovaps %xmm0, 32(%rsp)
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vmovaps 16(%rsp), %xmm0
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vmovaps (%rsp), %xmm1
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call HIDDEN_JUMPTARGET(\callee)
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vmovaps %xmm0, %xmm1
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vmovaps 32(%rsp), %xmm0
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vinsertf128 $1, %xmm1, %ymm0, %ymm0
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movq %rbp, %rsp
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cfi_def_cfa_register (%rsp)
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popq %rbp
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cfi_adjust_cfa_offset (-8)
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cfi_restore (%rbp)
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ret
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.endm
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/* 3 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */
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.macro WRAPPER_IMPL_AVX_fFF callee
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pushq %rbp
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cfi_adjust_cfa_offset (8)
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cfi_rel_offset (%rbp, 0)
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movq %rsp, %rbp
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cfi_def_cfa_register (%rbp)
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andq $-32, %rsp
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pushq %r13
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cfi_adjust_cfa_offset (8)
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cfi_rel_offset (%r13, 0)
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pushq %r14
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cfi_adjust_cfa_offset (8)
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cfi_rel_offset (%r14, 0)
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subq $48, %rsp
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movq %rsi, %r14
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movq %rdi, %r13
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vextractf128 $1, %ymm0, 32(%rsp)
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vzeroupper
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call HIDDEN_JUMPTARGET(\callee)
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vmovaps 32(%rsp), %xmm0
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lea (%rsp), %rdi
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lea 16(%rsp), %rsi
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call HIDDEN_JUMPTARGET(\callee)
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vmovapd (%rsp), %xmm0
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vmovapd 16(%rsp), %xmm1
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vmovapd %xmm0, 16(%r13)
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vmovapd %xmm1, 16(%r14)
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addq $48, %rsp
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popq %r14
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cfi_adjust_cfa_offset (-8)
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cfi_restore (%r14)
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popq %r13
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cfi_adjust_cfa_offset (-8)
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cfi_restore (%r13)
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movq %rbp, %rsp
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cfi_def_cfa_register (%rsp)
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popq %rbp
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cfi_adjust_cfa_offset (-8)
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cfi_restore (%rbp)
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ret
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.endm
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/* AVX512 ISA version as wrapper to AVX2 ISA version. */
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.macro WRAPPER_IMPL_AVX512 callee
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pushq %rbp
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cfi_adjust_cfa_offset (8)
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cfi_rel_offset (%rbp, 0)
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movq %rsp, %rbp
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cfi_def_cfa_register (%rbp)
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andq $-64, %rsp
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subq $64, %rsp
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/* Below is encoding for vmovaps %zmm0, (%rsp). */
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.byte 0x62
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.byte 0xf1
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.byte 0x7c
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.byte 0x48
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.byte 0x29
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.byte 0x04
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.byte 0x24
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/* Below is encoding for vmovapd (%rsp), %ymm0. */
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.byte 0xc5
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.byte 0xfd
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.byte 0x28
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.byte 0x04
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.byte 0x24
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call HIDDEN_JUMPTARGET(\callee)
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/* Below is encoding for vmovapd 32(%rsp), %ymm0. */
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.byte 0xc5
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.byte 0xfd
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.byte 0x28
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.byte 0x44
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.byte 0x24
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.byte 0x20
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call HIDDEN_JUMPTARGET(\callee)
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movq %rbp, %rsp
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cfi_def_cfa_register (%rsp)
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popq %rbp
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cfi_adjust_cfa_offset (-8)
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cfi_restore (%rbp)
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ret
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.endm
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/* 2 argument AVX512 ISA version as wrapper to AVX2 ISA version. */
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.macro WRAPPER_IMPL_AVX512_ff callee
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pushq %rbp
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cfi_adjust_cfa_offset (8)
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cfi_rel_offset (%rbp, 0)
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movq %rsp, %rbp
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cfi_def_cfa_register (%rbp)
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andq $-64, %rsp
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subq $128, %rsp
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/* Below is encoding for vmovaps %zmm0, (%rsp). */
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.byte 0x62
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.byte 0xf1
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.byte 0x7c
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.byte 0x48
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.byte 0x29
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.byte 0x04
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.byte 0x24
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/* Below is encoding for vmovaps %zmm1, 64(%rsp). */
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.byte 0x62
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.byte 0xf1
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.byte 0x7c
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.byte 0x48
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.byte 0x29
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.byte 0x4c
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.byte 0x24
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/* Below is encoding for vmovapd (%rsp), %ymm0. */
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.byte 0xc5
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.byte 0xfd
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.byte 0x28
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.byte 0x04
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.byte 0x24
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/* Below is encoding for vmovapd 64(%rsp), %ymm1. */
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.byte 0xc5
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.byte 0xfd
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.byte 0x28
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.byte 0x4c
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.byte 0x24
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.byte 0x40
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call HIDDEN_JUMPTARGET(\callee)
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/* Below is encoding for vmovapd 32(%rsp), %ymm0. */
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.byte 0xc5
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.byte 0xfd
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.byte 0x28
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.byte 0x44
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.byte 0x24
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.byte 0x20
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/* Below is encoding for vmovapd 96(%rsp), %ymm1. */
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.byte 0xc5
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.byte 0xfd
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.byte 0x28
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.byte 0x4c
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.byte 0x24
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.byte 0x60
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call HIDDEN_JUMPTARGET(\callee)
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movq %rbp, %rsp
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cfi_def_cfa_register (%rsp)
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popq %rbp
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cfi_adjust_cfa_offset (-8)
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cfi_restore (%rbp)
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ret
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.endm
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/* 3 argument AVX512 ISA version as wrapper to AVX2 ISA version. */
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.macro WRAPPER_IMPL_AVX512_fFF callee
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pushq %rbp
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cfi_adjust_cfa_offset (8)
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cfi_rel_offset (%rbp, 0)
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movq %rsp, %rbp
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cfi_def_cfa_register (%rbp)
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andq $-64, %rsp
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pushq %r12
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cfi_adjust_cfa_offset (8)
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cfi_rel_offset (%r12, 0)
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pushq %r13
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cfi_adjust_cfa_offset (8)
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cfi_rel_offset (%r13, 0)
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subq $176, %rsp
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movq %rsi, %r13
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/* Below is encoding for vmovaps %zmm0, (%rsp). */
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.byte 0x62
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.byte 0xf1
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.byte 0x7c
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.byte 0x48
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.byte 0x29
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.byte 0x04
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.byte 0x24
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movq %rdi, %r12
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/* Below is encoding for vmovapd (%rsp), %ymm0. */
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.byte 0xc5
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.byte 0xfd
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.byte 0x28
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.byte 0x04
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.byte 0x24
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call HIDDEN_JUMPTARGET(\callee)
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/* Below is encoding for vmovapd 32(%rsp), %ymm0. */
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.byte 0xc5
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.byte 0xfd
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.byte 0x28
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.byte 0x44
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.byte 0x24
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.byte 0x20
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lea 64(%rsp), %rdi
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lea 96(%rsp), %rsi
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call HIDDEN_JUMPTARGET(\callee)
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/* Below is encoding for vmovapd 64(%rsp), %ymm0. */
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.byte 0xc5
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.byte 0xfd
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.byte 0x28
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.byte 0x44
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.byte 0x24
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.byte 0x40
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/* Below is encoding for vmovapd 96(%rsp), %ymm1. */
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.byte 0xc5
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.byte 0xfd
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.byte 0x28
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.byte 0x4c
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.byte 0x24
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.byte 0x60
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/* Below is encoding for vmovapd %ymm0, 32(%r12). */
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.byte 0xc4
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.byte 0xc1
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.byte 0x7d
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.byte 0x29
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.byte 0x44
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.byte 0x24
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.byte 0x20
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/* Below is encoding for vmovapd %ymm1, 32(%r13). */
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.byte 0xc4
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.byte 0xc1
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.byte 0x7d
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.byte 0x29
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.byte 0x4d
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.byte 0x20
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addq $176, %rsp
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popq %r13
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cfi_adjust_cfa_offset (-8)
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cfi_restore (%r13)
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popq %r12
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cfi_adjust_cfa_offset (-8)
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cfi_restore (%r12)
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movq %rbp, %rsp
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cfi_def_cfa_register (%rsp)
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popq %rbp
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cfi_adjust_cfa_offset (-8)
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cfi_restore (%rbp)
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ret
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.endm
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