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If assembler doesn't support AVX512DQ, _dl_runtime_resolve_avx is used to save the first 8 vector registers, which only saves the lower 256 bits of vector register, for lazy binding. When it is called on AVX512 platform, the upper 256 bits of ZMM registers are clobbered. Parameters passed in ZMM registers will be wrong when the function is called the first time. This patch requires binutils 2.24, whose assembler can store and load ZMM registers, to build x86-64 glibc. Since mathvec library needs assembler support for AVX512DQ, we disable mathvec if assembler doesn't support AVX512DQ. [BZ #20139] * config.h.in (HAVE_AVX512_ASM_SUPPORT): Renamed to ... (HAVE_AVX512DQ_ASM_SUPPORT): This. * sysdeps/x86_64/configure.ac: Require assembler from binutils 2.24 or above. (HAVE_AVX512_ASM_SUPPORT): Removed. (HAVE_AVX512DQ_ASM_SUPPORT): New. * sysdeps/x86_64/configure: Regenerated. * sysdeps/x86_64/dl-trampoline.S: Make HAVE_AVX512_ASM_SUPPORT check unconditional. * sysdeps/x86_64/multiarch/ifunc-impl-list.c: Likewise. * sysdeps/x86_64/multiarch/memcpy.S: Likewise. * sysdeps/x86_64/multiarch/memcpy_chk.S: Likewise. * sysdeps/x86_64/multiarch/memmove-avx512-no-vzeroupper.S: Likewise. * sysdeps/x86_64/multiarch/memmove-avx512-unaligned-erms.S: Likewise. * sysdeps/x86_64/multiarch/memmove.S: Likewise. * sysdeps/x86_64/multiarch/memmove_chk.S: Likewise. * sysdeps/x86_64/multiarch/mempcpy.S: Likewise. * sysdeps/x86_64/multiarch/mempcpy_chk.S: Likewise. * sysdeps/x86_64/multiarch/memset-avx512-no-vzeroupper.S: Likewise. * sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S: Likewise. * sysdeps/x86_64/multiarch/memset.S: Likewise. * sysdeps/x86_64/multiarch/memset_chk.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core_avx512.S: Check HAVE_AVX512DQ_ASM_SUPPORT instead of HAVE_AVX512_ASM_SUPPORT. * sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx51: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core_avx512.S: Likewise.
71 lines
2.2 KiB
ArmAsm
71 lines
2.2 KiB
ArmAsm
/* Multiple versions of __mempcpy_chk
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All versions must be listed in ifunc-impl-list.c.
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Copyright (C) 2010-2016 Free Software Foundation, Inc.
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Contributed by Intel Corporation.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include <init-arch.h>
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/* Define multiple versions only for the definition in lib and for
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DSO. There are no multiarch mempcpy functions for static binaries.
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*/
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#if IS_IN (libc)
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# ifdef SHARED
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.text
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ENTRY(__mempcpy_chk)
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.type __mempcpy_chk, @gnu_indirect_function
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LOAD_RTLD_GLOBAL_RO_RDX
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HAS_ARCH_FEATURE (AVX512F_Usable)
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jz 1f
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lea __mempcpy_chk_avx512_no_vzeroupper(%rip), %RAX_LP
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HAS_ARCH_FEATURE (Prefer_No_VZEROUPPER)
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jnz 2f
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lea __mempcpy_chk_avx512_unaligned_erms(%rip), %RAX_LP
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HAS_CPU_FEATURE (ERMS)
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jnz 2f
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lea __mempcpy_chk_avx512_unaligned(%rip), %RAX_LP
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ret
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1: lea __mempcpy_chk_avx_unaligned(%rip), %RAX_LP
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HAS_ARCH_FEATURE (AVX_Fast_Unaligned_Load)
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jz L(Fast_Unaligned_Load)
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HAS_CPU_FEATURE (ERMS)
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jz 2f
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lea __mempcpy_chk_avx_unaligned_erms(%rip), %RAX_LP
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ret
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L(Fast_Unaligned_Load):
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lea __mempcpy_chk_sse2_unaligned(%rip), %RAX_LP
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HAS_ARCH_FEATURE (Fast_Unaligned_Copy)
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jz L(SSSE3)
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HAS_CPU_FEATURE (ERMS)
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jz 2f
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lea __mempcpy_chk_sse2_unaligned_erms(%rip), %RAX_LP
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ret
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L(SSSE3):
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HAS_CPU_FEATURE (SSSE3)
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jz 2f
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lea __mempcpy_chk_ssse3_back(%rip), %RAX_LP
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HAS_ARCH_FEATURE (Fast_Copy_Backward)
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jnz 2f
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lea __mempcpy_chk_ssse3(%rip), %RAX_LP
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2: ret
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END(__mempcpy_chk)
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# else
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# include "../mempcpy_chk.S"
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# endif
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#endif
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