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2002-06-05 Brian Youmans <3diff@gnu.org> * sysdeps/ia64/fpu/e_acos.S: Added text of Intel license. * sysdeps/ia64/fpu/e_acosf.S: Likewise. * sysdeps/ia64/fpu/e_acosl.S: Likewise. * sysdeps/ia64/fpu/e_asin.S: Likewise. * sysdeps/ia64/fpu/e_asinf.S: Likewise. * sysdeps/ia64/fpu/e_asinl.S: Likewise. * sysdeps/ia64/fpu/e_atan2.S: Likewise. * sysdeps/ia64/fpu/e_atan2f.S: Likewise. * sysdeps/ia64/fpu/e_cosh.S: Likewise. * sysdeps/ia64/fpu/e_coshf.S: Likewise. * sysdeps/ia64/fpu/e_coshl.S: Likewise. * sysdeps/ia64/fpu/e_exp.S: Likewise. * sysdeps/ia64/fpu/e_expf.S: Likewise. * sysdeps/ia64/fpu/e_fmod.S: Likewise. * sysdeps/ia64/fpu/e_fmodf.S: Likewise. * sysdeps/ia64/fpu/e_fmodl.S: Likewise. * sysdeps/ia64/fpu/e_hypot.S: Likewise. * sysdeps/ia64/fpu/e_hypotf.S: Likewise. * sysdeps/ia64/fpu/e_hypotl.S: Likewise. * sysdeps/ia64/fpu/e_log.S: Likewise. * sysdeps/ia64/fpu/e_logf.S: Likewise. * sysdeps/ia64/fpu/e_pow.S: Likewise. * sysdeps/ia64/fpu/e_powf.S: Likewise. * sysdeps/ia64/fpu/e_powl.S: Likewise. * sysdeps/ia64/fpu/e_remainder.S: Likewise. * sysdeps/ia64/fpu/e_remainderf.S: Likewise. * sysdeps/ia64/fpu/e_remainderl.S: Likewise. * sysdeps/ia64/fpu/e_scalb.S: Likewise. * sysdeps/ia64/fpu/e_scalbf.S: Likewise. * sysdeps/ia64/fpu/e_scalbl.S: Likewise. * sysdeps/ia64/fpu/e_sinh.S: Likewise. * sysdeps/ia64/fpu/e_sinhf.S: Likewise. * sysdeps/ia64/fpu/e_sinhl.S: Likewise. * sysdeps/ia64/fpu/e_sqrt.S: Likewise. * sysdeps/ia64/fpu/e_sqrtf.S: Likewise. * sysdeps/ia64/fpu/e_sqrtl.S: Likewise. * sysdeps/ia64/fpu/libm_atan2_req.S: Likewise. * sysdeps/ia64/fpu/libm_error.c: Likewise. * sysdeps/ia64/fpu/libm_frexp4.S: Likewise. * sysdeps/ia64/fpu/libm_frexp4f.S: Likewise. * sysdeps/ia64/fpu/s_frexpl.c: Likewise. * sysdeps/ia64/fpu/s_ilogb.S: Likewise. * sysdeps/ia64/fpu/s_ilogbf.S: Likewise. * sysdeps/ia64/fpu/s_ilogbl.S: Likewise. * sysdeps/ia64/fpu/s_ldexp.S: Likewise. * sysdeps/ia64/fpu/s_ldexpf.S: Likewise. * sysdeps/ia64/fpu/s_ldexpl.S: Likewise. * sysdeps/ia64/fpu/s_log1p.S: Likewise. * sysdeps/ia64/fpu/s_log1pf.S: Likewise. * sysdeps/ia64/fpu/s_log1pl.S: Likewise. * sysdeps/ia64/fpu/s_logb.S: Likewise. * sysdeps/ia64/fpu/s_logbf.S: Likewise. * sysdeps/ia64/fpu/s_logbl.S: Likewise. * sysdeps/ia64/fpu/s_modf.S: Likewise. * sysdeps/ia64/fpu/s_modff.S: Likewise. * sysdeps/ia64/fpu/s_modfl.S: Likewise. * sysdeps/ia64/fpu/s_nearbyint.S: Likewise. * sysdeps/ia64/fpu/s_nearbyintf.S: Likewise. * sysdeps/ia64/fpu/s_nearbyintl.S: Likewise. * sysdeps/ia64/fpu/s_rint.S: Likewise. * sysdeps/ia64/fpu/s_rintf.S: Likewise. * sysdeps/ia64/fpu/s_rintl.S: Likewise. * sysdeps/ia64/fpu/s_round.S: Likewise. * sysdeps/ia64/fpu/s_roundf.S: Likewise. * sysdeps/ia64/fpu/s_roundl.S: Likewise. * sysdeps/ia64/fpu/s_scalbn.S: Likewise. * sysdeps/ia64/fpu/s_scalbnf.S: Likewise. * sysdeps/ia64/fpu/s_scalbnl.S: Likewise. * sysdeps/ia64/fpu/s_significand.S: Likewise. * sysdeps/ia64/fpu/s_significandf.S: Likewise. * sysdeps/ia64/fpu/s_significandl.S: Likewise. * sysdeps/ia64/fpu/s_tan.S: Likewise. * sysdeps/ia64/fpu/s_tanf.S: Likewise. * sysdeps/ia64/fpu/s_tanl.S: Likewise. * sysdeps/ia64/fpu/s_trunc.S: Likewise. * sysdeps/ia64/fpu/s_truncf.S: Likewise. * sysdeps/ia64/fpu/s_truncl.S: Likewise. * sysdeps/ieee754/dbl-64/doasin.c: Changed copyright notice to reflect IBM donation of math library to FSF * sysdeps/ieee754/dbl-64/dosincos.c: Likewise. * sysdeps/ieee754/dbl-64/e_asin.c: Likewise. * sysdeps/ieee754/dbl-64/e_atan2.c: Likewise. * sysdeps/ieee754/dbl-64/e_exp.c: Likewise. * sysdeps/ieee754/dbl-64/e_log.c: Likewise. * sysdeps/ieee754/dbl-64/e_pow.c: Likewise. * sysdeps/ieee754/dbl-64/e_remainder.c: Likewise. * sysdeps/ieee754/dbl-64/e_sqrt.c: Likewise. * sysdeps/ieee754/dbl-64/halfulp.c: Likewise. * sysdeps/ieee754/dbl-64/mpa.c: Likewise. * sysdeps/ieee754/dbl-64/mpatan.c: Likewise. * sysdeps/ieee754/dbl-64/mpatan2.c: Likewise. * sysdeps/ieee754/dbl-64/mpexp.c: Likewise. * sysdeps/ieee754/dbl-64/mplog.c: Likewise. * sysdeps/ieee754/dbl-64/mpsqrt.c: Likewise. * sysdeps/ieee754/dbl-64/mptan.c: Likewise. * sysdeps/ieee754/dbl-64/s_atan.c: Likewise. * sysdeps/ieee754/dbl-64/s_sin.c: Likewise. * sysdeps/ieee754/dbl-64/s_tan.c: Likewise. * sysdeps/ieee754/dbl-64/sincos32.c: Likewise. * sysdeps/ieee754/dbl-64/slowexp.c: Likewise. * sysdeps/ieee754/dbl-64/slowpow.c: Likewise. * sysdeps/gnu/netinet/udp.h: Added BSD copying permission notice * sysdeps/vax/__longjmp.c: Likewise. * sysdeps/vax/setjmp.c: Likewise. * libio/filedoalloc.c: Fixed BSD copying permission notice to remove advertising clause * sysdeps/vax/htonl.s: Likewise. * sysdeps/vax/htons.s: Likewise. * libio/wfiledoalloc.c: Likewise. * stdlib/random.c: Likewise. * stdlib/random_r.c: Likewise. * sysdeps/mach/sys/reboot.h: Likewise. * inet/getnameinfo.c: Deleted advertising clause from Inner Net License * sysdeps/posix/getaddrinfo.c: Likewise. * sunrpc/des_impl.c: Updated license permission notice to Lesser GPL and corrected pointer to point to the correct license.
565 lines
12 KiB
ArmAsm
565 lines
12 KiB
ArmAsm
.file "scalb.s"
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// Copyright (C) 2000, 2001, Intel Corporation
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// All rights reserved.
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//
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// Contributed 2/2/2000 by John Harrison, Ted Kubaska, Bob Norin, Shane Story,
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// and Ping Tak Peter Tang of the Computational Software Lab, Intel Corporation.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// * The name of Intel Corporation may not be used to endorse or promote
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// products derived from this software without specific prior written
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// permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Intel Corporation is the author of this code, and requests that all
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// problem reports or change requests be submitted to it directly at
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// http://developer.intel.com/opensource.
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//
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// History
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//==============================================================
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// 2/02/00 Initial version
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// 1/26/01 Scalb completely reworked and now standalone version
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//
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// API
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//==============================================================
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// double = scalb (double x, double n)
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// input floating point f8 and floating point f9
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// output floating point f8
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//
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// Returns x* 2**n using an fma and detects overflow
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// and underflow.
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//
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//
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#include "libm_support.h"
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FR_Floating_X = f8
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FR_Result = f8
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FR_Floating_N = f9
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FR_Result2 = f9
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FR_Norm_N = f10
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FR_Result3 = f11
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FR_Norm_X = f12
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FR_N_float_int = f13
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FR_Two_N = f14
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FR_Two_to_Big = f15
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FR_Big = f6
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FR_NBig = f7
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GR_N_Biased = r15
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GR_Big = r16
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GR_NBig = r17
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GR_Scratch = r18
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GR_Scratch1 = r19
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GR_Bias = r20
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GR_N_as_int = r21
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GR_SAVE_B0 = r32
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GR_SAVE_GP = r33
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GR_SAVE_PFS = r34
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GR_Parameter_X = r35
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GR_Parameter_Y = r36
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GR_Parameter_RESULT = r37
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GR_Tag = r38
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.align 32
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.global scalb
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.section .text
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.proc scalb
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.align 32
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scalb:
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#ifdef _LIBC
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.global __ieee754_scalb
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.type __ieee754_scalb,@function
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__ieee754_scalb:
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#endif
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//
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// Is x NAN, INF, ZERO, +-?
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//
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{ .mfi
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alloc r32=ar.pfs,0,3,4,0
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fclass.m.unc p7,p0 = FR_Floating_X, 0xe7 //@snan | @qnan | @inf | @zero
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addl GR_Scratch = 0x019C3F,r0
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}
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//
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// Is y a NAN, INF, ZERO, +-?
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//
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{ .mfi
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nop.m 999
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fclass.m.unc p6,p0 = FR_Floating_N, 0xe7 //@snan | @qnan | @inf | @zero
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addl GR_Scratch1 = 0x063BF,r0
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}
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;;
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//
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// Convert N to a fp integer
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// Normalize x
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//
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{ .mfi
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nop.m 0
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fnorm.s1 FR_Norm_N = FR_Floating_N
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nop.i 999
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}
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{ .mfi
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nop.m 999
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fnorm.s1 FR_Norm_X = FR_Floating_X
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nop.i 999
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};;
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//
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// Create 2*big
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// Create 2**-big
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// Normalize x
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// Branch on special values.
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//
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{ .mib
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setf.exp FR_Big = GR_Scratch
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nop.i 0
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(p6) br.cond.spnt L(SCALB_NAN_INF_ZERO)
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}
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{ .mib
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setf.exp FR_NBig = GR_Scratch1
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nop.i 0
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(p7) br.cond.spnt L(SCALB_NAN_INF_ZERO)
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};;
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//
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// Convert N to a fp integer
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// Create -35000
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//
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{ .mfi
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addl GR_Scratch = 1,r0
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fcvt.fx.trunc.s1 FR_N_float_int = FR_Norm_N
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addl GR_NBig = -35000,r0
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}
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;;
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//
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// Put N if a GP register
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// Convert N_float_int to floating point value
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// Create 35000
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// Build the exponent Bias
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//
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{ .mii
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getf.sig GR_N_as_int = FR_N_float_int
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shl GR_Scratch = GR_Scratch,63
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addl GR_Big = 35000,r0
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}
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{ .mfi
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addl GR_Bias = 0x0FFFF,r0
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fcvt.xf FR_N_float_int = FR_N_float_int
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nop.i 0
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};;
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//
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// Catch those fp values that are beyond 2**64-1
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// Is N > 35000
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// Is N < -35000
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//
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{ .mfi
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cmp.ne.unc p9,p10 = GR_N_as_int,GR_Scratch
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nop.f 0
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nop.i 0
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}
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{ .mmi
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cmp.ge.unc p6, p0 = GR_N_as_int, GR_Big
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cmp.le.unc p8, p0 = GR_N_as_int, GR_NBig
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nop.i 0
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};;
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//
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// Is N really an int, only for those non-int indefinites?
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// Create exp bias.
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//
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{ .mfi
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add GR_N_Biased = GR_Bias,GR_N_as_int
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(p9) fcmp.neq.unc.s1 p7,p0 = FR_Norm_N, FR_N_float_int
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nop.i 0
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};;
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//
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// Branch and return if N is not an int.
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// Main path, create 2**N
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//
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{ .mfi
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setf.exp FR_Two_N = GR_N_Biased
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nop.i 999
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}
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{ .mfb
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nop.m 0
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(p7) frcpa f8,p11 = f0,f0
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(p7) br.ret.spnt b0
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};;
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//
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// Set denormal on denormal input x and denormal input N
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//
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{ .mfi
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nop.m 999
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(p10)fcmp.ge.s1 p6,p8 = FR_Norm_N,f0
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nop.i 0
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};;
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{ .mfi
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nop.m 999
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fcmp.ge.s0 p0,p11 = FR_Floating_X,f0
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nop.i 999
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}
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{ .mfi
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nop.m 999
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fcmp.ge.s0 p12,p13 = FR_Floating_N,f0
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nop.i 0
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};;
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//
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// Adjust 2**N if N was very small or very large
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//
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{ .mfi
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nop.m 0
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(p6) fma.s1 FR_Two_N = FR_Big,f1,f0
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nop.i 0
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}
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{ .mlx
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nop.m 999
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(p0) movl GR_Scratch = 0x00000000000303FF
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};;
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{ .mfi
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nop.m 0
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(p8) fma.s1 FR_Two_N = FR_NBig,f1,f0
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nop.i 0
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}
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{ .mlx
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nop.m 999
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(p0) movl GR_Scratch1= 0x00000000000103FF
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};;
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// Set up necessary status fields
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//
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// S0 user supplied status
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// S2 user supplied status + WRE + TD (Overflows)
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// S3 user supplied status + FZ + TD (Underflows)
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//
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{ .mfi
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nop.m 999
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(p0) fsetc.s3 0x7F,0x41
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nop.i 999
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}
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{ .mfi
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nop.m 999
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(p0) fsetc.s2 0x7F,0x42
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nop.i 999
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};;
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//
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// Do final operation
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//
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{ .mfi
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setf.exp FR_NBig = GR_Scratch
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fma.d.s0 FR_Result = FR_Two_N,FR_Norm_X,f0
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nop.i 999
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}
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{ .mfi
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nop.m 999
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fma.d.s3 FR_Result3 = FR_Two_N,FR_Norm_X,f0
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nop.i 999
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};;
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{ .mfi
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setf.exp FR_Big = GR_Scratch1
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fma.d.s2 FR_Result2 = FR_Two_N,FR_Norm_X,f0
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nop.i 999
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};;
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// Check for overflow or underflow.
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//
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// S0 user supplied status
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// S2 user supplied status + WRE + TD (Overflow)
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// S3 user supplied status + FZ + TD (Underflow)
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//
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//
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// Restore s3
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// Restore s2
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//
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{ .mfi
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nop.m 0
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fsetc.s3 0x7F,0x40
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nop.i 999
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}
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{ .mfi
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nop.m 0
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fsetc.s2 0x7F,0x40
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nop.i 999
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};;
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//
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// Is the result zero?
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//
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{ .mfi
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nop.m 999
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fclass.m.unc p6, p0 = FR_Result3, 0x007
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nop.i 999
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}
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{ .mfi
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addl GR_Tag = 53, r0
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fcmp.ge.unc.s1 p7, p8 = FR_Result2 , FR_Big
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nop.i 0
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};;
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//
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// Detect masked underflow - Tiny + Inexact Only
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//
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{ .mfi
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nop.m 999
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(p6) fcmp.neq.unc.s1 p6, p0 = FR_Result , FR_Result2
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nop.i 999
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};;
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//
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// Is result bigger the allowed range?
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// Branch out for underflow
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//
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{ .mfb
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(p6) addl GR_Tag = 54, r0
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(p8) fcmp.le.unc.s1 p9, p10 = FR_Result2 , FR_NBig
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(p6) br.cond.spnt L(SCALB_UNDERFLOW)
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};;
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//
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// Branch out for overflow
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//
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{ .mbb
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nop.m 0
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(p7) br.cond.spnt L(SCALB_OVERFLOW)
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(p9) br.cond.spnt L(SCALB_OVERFLOW)
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};;
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//
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// Return from main path.
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//
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{ .mfb
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nop.m 999
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nop.f 0
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br.ret.sptk b0;;
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}
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L(SCALB_NAN_INF_ZERO):
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//
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// Convert N to a fp integer
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//
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{ .mfi
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addl GR_Scratch = 1,r0
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fcvt.fx.trunc.s1 FR_N_float_int = FR_Norm_N
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nop.i 999
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}
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{ .mfi
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nop.m 0
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fclass.m.unc p6,p0 = FR_Floating_N, 0xc3 //@snan | @qnan
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nop.i 0
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};;
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{ .mfi
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nop.m 0
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fclass.m.unc p7,p0 = FR_Floating_X, 0xc3 //@snan | @qnan
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shl GR_Scratch = GR_Scratch,63
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};;
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{ .mfi
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nop.m 0
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|
fclass.m.unc p8,p0 = FR_Floating_N, 0x21 // @inf
|
|
nop.i 0
|
|
}
|
|
{ .mfi
|
|
nop.m 0
|
|
fclass.m.unc p9,p0 = FR_Floating_N, 0x22 // @-inf
|
|
nop.i 0
|
|
};;
|
|
|
|
//
|
|
// Either X or N is a Nan, return result and possible raise invalid.
|
|
//
|
|
{ .mfb
|
|
nop.m 0
|
|
(p6) fma.d.s0 FR_Result = FR_Floating_N,FR_Floating_X,f0
|
|
(p6) br.ret.spnt b0
|
|
};;
|
|
{ .mfb
|
|
getf.sig GR_N_as_int = FR_N_float_int
|
|
(p7) fma.d.s0 FR_Result = FR_Floating_N,FR_Floating_X,f0
|
|
(p7) br.ret.spnt b0
|
|
};;
|
|
|
|
//
|
|
// If N + Inf do something special
|
|
// For N = -Inf, create Int
|
|
//
|
|
{ .mfb
|
|
nop.m 0
|
|
(p8) fma.d.s0 FR_Result = FR_Floating_X, FR_Floating_N,f0
|
|
(p8) br.ret.spnt b0
|
|
}
|
|
{ .mfi
|
|
nop.m 0
|
|
(p9) fnma.d.s0 FR_Floating_N = FR_Floating_N, f1, f0
|
|
nop.i 0
|
|
};;
|
|
|
|
//
|
|
// If N==-Inf,return x/(-N)
|
|
//
|
|
{ .mfb
|
|
nop.m 0
|
|
(p9) frcpa.s0 FR_Result,p6 = FR_Floating_X,FR_Floating_N
|
|
(p9) br.ret.spnt b0
|
|
};;
|
|
|
|
//
|
|
// Convert N_float_int to floating point value
|
|
//
|
|
{ .mfi
|
|
cmp.ne.unc p9,p0 = GR_N_as_int,GR_Scratch
|
|
fcvt.xf FR_N_float_int = FR_N_float_int
|
|
nop.i 0
|
|
};;
|
|
|
|
//
|
|
// Is N an integer.
|
|
//
|
|
{ .mfi
|
|
nop.m 0
|
|
(p9) fcmp.neq.unc.s1 p7,p0 = FR_Norm_N, FR_N_float_int
|
|
nop.i 0
|
|
};;
|
|
|
|
//
|
|
// If N not an int, return NaN and raise invalid.
|
|
//
|
|
{ .mfb
|
|
nop.m 0
|
|
(p7) frcpa.s0 FR_Result,p6 = f0,f0
|
|
(p7) br.ret.spnt b0
|
|
};;
|
|
|
|
//
|
|
// Always return x in other path.
|
|
//
|
|
{ .mfb
|
|
nop.m 0
|
|
fma.d.s0 FR_Result = FR_Floating_X,f1,f0
|
|
br.ret.sptk b0
|
|
};;
|
|
|
|
.endp scalb
|
|
ASM_SIZE_DIRECTIVE(scalb)
|
|
#ifdef _LIBC
|
|
ASM_SIZE_DIRECTIVE(__ieee754_scalb)
|
|
#endif
|
|
.proc __libm_error_region
|
|
__libm_error_region:
|
|
|
|
L(SCALB_OVERFLOW):
|
|
L(SCALB_UNDERFLOW):
|
|
|
|
//
|
|
// Get stack address of N
|
|
//
|
|
.prologue
|
|
{ .mfi
|
|
add GR_Parameter_Y=-32,sp
|
|
nop.f 0
|
|
.save ar.pfs,GR_SAVE_PFS
|
|
mov GR_SAVE_PFS=ar.pfs
|
|
}
|
|
//
|
|
// Adjust sp
|
|
//
|
|
{ .mfi
|
|
.fframe 64
|
|
add sp=-64,sp
|
|
nop.f 0
|
|
mov GR_SAVE_GP=gp
|
|
};;
|
|
|
|
//
|
|
// Store N on stack in correct position
|
|
// Locate the address of x on stack
|
|
//
|
|
{ .mmi
|
|
stfd [GR_Parameter_Y] = FR_Norm_N,16
|
|
add GR_Parameter_X = 16,sp
|
|
.save b0, GR_SAVE_B0
|
|
mov GR_SAVE_B0=b0
|
|
};;
|
|
|
|
//
|
|
// Store x on the stack.
|
|
// Get address for result on stack.
|
|
//
|
|
.body
|
|
{ .mib
|
|
stfd [GR_Parameter_X] = FR_Norm_X
|
|
add GR_Parameter_RESULT = 0,GR_Parameter_Y
|
|
nop.b 0
|
|
}
|
|
{ .mib
|
|
stfd [GR_Parameter_Y] = FR_Result
|
|
add GR_Parameter_Y = -16,GR_Parameter_Y
|
|
br.call.sptk b0=__libm_error_support#
|
|
};;
|
|
|
|
//
|
|
// Get location of result on stack
|
|
//
|
|
{ .mmi
|
|
nop.m 0
|
|
nop.m 0
|
|
add GR_Parameter_RESULT = 48,sp
|
|
};;
|
|
|
|
//
|
|
// Get the new result
|
|
//
|
|
{ .mmi
|
|
ldfd FR_Result = [GR_Parameter_RESULT]
|
|
.restore sp
|
|
add sp = 64,sp
|
|
mov b0 = GR_SAVE_B0
|
|
};;
|
|
|
|
//
|
|
// Restore gp, ar.pfs and return
|
|
//
|
|
{ .mib
|
|
mov gp = GR_SAVE_GP
|
|
mov ar.pfs = GR_SAVE_PFS
|
|
br.ret.sptk b0
|
|
};;
|
|
|
|
.endp __libm_error_region
|
|
ASM_SIZE_DIRECTIVE(__libm_error_region)
|
|
|
|
.type __libm_error_support#,@function
|
|
.global __libm_error_support#
|