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2b778ceb40
I used these shell commands: ../glibc/scripts/update-copyrights $PWD/../gnulib/build-aux/update-copyright (cd ../glibc && git commit -am"[this commit message]") and then ignored the output, which consisted lines saying "FOO: warning: copyright statement not found" for each of 6694 files FOO. I then removed trailing white space from benchtests/bench-pthread-locks.c and iconvdata/tst-iconv-big5-hkscs-to-2ucs4.c, to work around this diagnostic from Savannah: remote: *** pre-commit check failed ... remote: *** error: lines with trailing whitespace found remote: error: hook declined to update refs/heads/master
48 lines
1.8 KiB
C
48 lines
1.8 KiB
C
/* Copyright (C) 2002-2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/* Default stack size. */
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#define ARCH_STACK_DEFAULT_SIZE (2 * 1024 * 1024)
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/* Minimum guard size. */
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#define ARCH_MIN_GUARD_SIZE 0
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/* Required stack pointer alignment at beginning. SSE requires 16
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bytes. */
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#define STACK_ALIGN 16
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/* Minimal stack size after allocating thread descriptor and guard size. */
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#define MINIMAL_REST_STACK 2048
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/* Alignment requirement for TCB.
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We need to store post-AVX vector registers in the TCB and we want the
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storage to be aligned to at least 32 bytes.
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Some processors such as Intel Atom pay a big penalty on every
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access using a segment override if that segment's base is not
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aligned to the size of a cache line. (See Intel 64 and IA-32
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Architectures Optimization Reference Manual, section 13.3.3.3,
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"Segment Base".) On such machines, a cache line is 64 bytes. */
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#define TCB_ALIGNMENT 64
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/* Location of current stack frame. The frame pointer is not usable. */
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#define CURRENT_STACK_FRAME \
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({ register char *frame __asm__("rsp"); frame; })
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