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af8ea0f449
Some extraneous semicolons were included in a recent patch which causes a build failure with newer compilers.
172 lines
4.8 KiB
C
172 lines
4.8 KiB
C
/* Shared HTM header. Emulate transactional execution facility intrinsics for
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compilers and assemblers that do not support the intrinsics and instructions
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yet.
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Copyright (C) 2015-2016 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _HTM_H
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#define _HTM_H 1
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#ifdef __ASSEMBLER__
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/* tbegin. */
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.macro TBEGIN
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.long 0x7c00051d
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.endm
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/* tend. 0 */
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.macro TEND
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.long 0x7c00055d
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.endm
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/* tabort. code */
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.macro TABORT code
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.byte 0x7c
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.byte \code
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.byte 0x07
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.byte 0x1d
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.endm
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/*"TEXASR - Transaction EXception And Summary Register"
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mfspr %dst,130 */
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.macro TEXASR dst
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mfspr \dst,130
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.endm
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#else
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#include <endian.h>
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/* Official HTM intrinsics interface matching GCC, but works
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on older GCC compatible compilers and binutils.
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We should somehow detect if the compiler supports it, because
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it may be able to generate slightly better code. */
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#define TBEGIN ".long 0x7c00051d"
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#define TEND ".long 0x7c00055d"
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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# define TABORT ".byte 0x1d,0x07,%1,0x7c"
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#else
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# define TABORT ".byte 0x7c,%1,0x07,0x1d"
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#endif
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#define __force_inline inline __attribute__((__always_inline__))
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#ifndef __HTM__
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#define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
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(((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1))
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#define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1)
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#define _tbegin() \
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({ unsigned int __ret; \
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asm volatile ( \
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TBEGIN "\t\n" \
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"mfcr %0\t\n" \
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"rlwinm %0,%0,3,1\t\n" \
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"xori %0,%0,1\t\n" \
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: "=r" (__ret) : \
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: "cr0", "memory"); \
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__ret; \
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})
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#define _tend() \
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({ unsigned int __ret; \
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asm volatile ( \
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TEND "\t\n" \
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"mfcr %0\t\n" \
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"rlwinm %0,%0,3,1\t\n" \
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"xori %0,%0,1\t\n" \
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: "=r" (__ret) : \
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: "cr0", "memory"); \
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__ret; \
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})
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#define _tabort(__code) \
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({ unsigned int __ret; \
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asm volatile ( \
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TABORT "\t\n" \
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"mfcr %0\t\n" \
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"rlwinm %0,%0,3,1\t\n" \
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"xori %0,%0,1\t\n" \
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: "=r" (__ret) : "r" (__code) \
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: "cr0", "memory"); \
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__ret; \
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})
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#define _texasru() \
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({ unsigned long __ret; \
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asm volatile ( \
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"mfspr %0,131\t\n" \
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: "=r" (__ret)); \
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__ret; \
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})
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#define __libc_tbegin(tdb) _tbegin ()
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#define __libc_tend(nested) _tend ()
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#define __libc_tabort(abortcode) _tabort (abortcode)
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#define __builtin_get_texasru() _texasru ()
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#else
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# include <htmintrin.h>
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# ifdef __TM_FENCE__
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/* New GCC behavior. */
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# define __libc_tbegin(R) __builtin_tbegin (R)
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# define __libc_tend(R) __builtin_tend (R)
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# define __libc_tabort(R) __builtin_tabort (R)
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# else
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/* Workaround an old GCC behavior. Earlier releases of GCC 4.9 and 5.0,
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didn't use to treat __builtin_tbegin, __builtin_tend and
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__builtin_tabort as compiler barriers, moving instructions into and
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out the transaction.
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Remove this when glibc drops support for GCC 5.0. */
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# define __libc_tbegin(R) \
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({ __asm__ volatile("" ::: "memory"); \
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unsigned int __ret = __builtin_tbegin (R); \
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__asm__ volatile("" ::: "memory"); \
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__ret; \
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})
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# define __libc_tabort(R) \
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({ __asm__ volatile("" ::: "memory"); \
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unsigned int __ret = __builtin_tabort (R); \
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__asm__ volatile("" ::: "memory"); \
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__ret; \
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})
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# define __libc_tend(R) \
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({ __asm__ volatile("" ::: "memory"); \
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unsigned int __ret = __builtin_tend (R); \
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__asm__ volatile("" ::: "memory"); \
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__ret; \
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})
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# endif /* __TM_FENCE__ */
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#endif /* __HTM__ */
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#endif /* __ASSEMBLER__ */
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/* Definitions used for TEXASR Failure code (bits 0:7). If the failure
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should be persistent, the abort code must be odd. 0xd0 through 0xff
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are reserved for the kernel and potential hypervisor. */
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#define _ABORT_PERSISTENT 0x01 /* An unspecified persistent abort. */
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#define _ABORT_LOCK_BUSY 0x34 /* Busy lock, not persistent. */
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#define _ABORT_NESTED_TRYLOCK (0x32 | _ABORT_PERSISTENT)
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#define _ABORT_SYSCALL (0x30 | _ABORT_PERSISTENT)
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#endif
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