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2002-06-05 Brian Youmans <3diff@gnu.org> * sysdeps/ia64/fpu/e_acos.S: Added text of Intel license. * sysdeps/ia64/fpu/e_acosf.S: Likewise. * sysdeps/ia64/fpu/e_acosl.S: Likewise. * sysdeps/ia64/fpu/e_asin.S: Likewise. * sysdeps/ia64/fpu/e_asinf.S: Likewise. * sysdeps/ia64/fpu/e_asinl.S: Likewise. * sysdeps/ia64/fpu/e_atan2.S: Likewise. * sysdeps/ia64/fpu/e_atan2f.S: Likewise. * sysdeps/ia64/fpu/e_cosh.S: Likewise. * sysdeps/ia64/fpu/e_coshf.S: Likewise. * sysdeps/ia64/fpu/e_coshl.S: Likewise. * sysdeps/ia64/fpu/e_exp.S: Likewise. * sysdeps/ia64/fpu/e_expf.S: Likewise. * sysdeps/ia64/fpu/e_fmod.S: Likewise. * sysdeps/ia64/fpu/e_fmodf.S: Likewise. * sysdeps/ia64/fpu/e_fmodl.S: Likewise. * sysdeps/ia64/fpu/e_hypot.S: Likewise. * sysdeps/ia64/fpu/e_hypotf.S: Likewise. * sysdeps/ia64/fpu/e_hypotl.S: Likewise. * sysdeps/ia64/fpu/e_log.S: Likewise. * sysdeps/ia64/fpu/e_logf.S: Likewise. * sysdeps/ia64/fpu/e_pow.S: Likewise. * sysdeps/ia64/fpu/e_powf.S: Likewise. * sysdeps/ia64/fpu/e_powl.S: Likewise. * sysdeps/ia64/fpu/e_remainder.S: Likewise. * sysdeps/ia64/fpu/e_remainderf.S: Likewise. * sysdeps/ia64/fpu/e_remainderl.S: Likewise. * sysdeps/ia64/fpu/e_scalb.S: Likewise. * sysdeps/ia64/fpu/e_scalbf.S: Likewise. * sysdeps/ia64/fpu/e_scalbl.S: Likewise. * sysdeps/ia64/fpu/e_sinh.S: Likewise. * sysdeps/ia64/fpu/e_sinhf.S: Likewise. * sysdeps/ia64/fpu/e_sinhl.S: Likewise. * sysdeps/ia64/fpu/e_sqrt.S: Likewise. * sysdeps/ia64/fpu/e_sqrtf.S: Likewise. * sysdeps/ia64/fpu/e_sqrtl.S: Likewise. * sysdeps/ia64/fpu/libm_atan2_req.S: Likewise. * sysdeps/ia64/fpu/libm_error.c: Likewise. * sysdeps/ia64/fpu/libm_frexp4.S: Likewise. * sysdeps/ia64/fpu/libm_frexp4f.S: Likewise. * sysdeps/ia64/fpu/s_frexpl.c: Likewise. * sysdeps/ia64/fpu/s_ilogb.S: Likewise. * sysdeps/ia64/fpu/s_ilogbf.S: Likewise. * sysdeps/ia64/fpu/s_ilogbl.S: Likewise. * sysdeps/ia64/fpu/s_ldexp.S: Likewise. * sysdeps/ia64/fpu/s_ldexpf.S: Likewise. * sysdeps/ia64/fpu/s_ldexpl.S: Likewise. * sysdeps/ia64/fpu/s_log1p.S: Likewise. * sysdeps/ia64/fpu/s_log1pf.S: Likewise. * sysdeps/ia64/fpu/s_log1pl.S: Likewise. * sysdeps/ia64/fpu/s_logb.S: Likewise. * sysdeps/ia64/fpu/s_logbf.S: Likewise. * sysdeps/ia64/fpu/s_logbl.S: Likewise. * sysdeps/ia64/fpu/s_modf.S: Likewise. * sysdeps/ia64/fpu/s_modff.S: Likewise. * sysdeps/ia64/fpu/s_modfl.S: Likewise. * sysdeps/ia64/fpu/s_nearbyint.S: Likewise. * sysdeps/ia64/fpu/s_nearbyintf.S: Likewise. * sysdeps/ia64/fpu/s_nearbyintl.S: Likewise. * sysdeps/ia64/fpu/s_rint.S: Likewise. * sysdeps/ia64/fpu/s_rintf.S: Likewise. * sysdeps/ia64/fpu/s_rintl.S: Likewise. * sysdeps/ia64/fpu/s_round.S: Likewise. * sysdeps/ia64/fpu/s_roundf.S: Likewise. * sysdeps/ia64/fpu/s_roundl.S: Likewise. * sysdeps/ia64/fpu/s_scalbn.S: Likewise. * sysdeps/ia64/fpu/s_scalbnf.S: Likewise. * sysdeps/ia64/fpu/s_scalbnl.S: Likewise. * sysdeps/ia64/fpu/s_significand.S: Likewise. * sysdeps/ia64/fpu/s_significandf.S: Likewise. * sysdeps/ia64/fpu/s_significandl.S: Likewise. * sysdeps/ia64/fpu/s_tan.S: Likewise. * sysdeps/ia64/fpu/s_tanf.S: Likewise. * sysdeps/ia64/fpu/s_tanl.S: Likewise. * sysdeps/ia64/fpu/s_trunc.S: Likewise. * sysdeps/ia64/fpu/s_truncf.S: Likewise. * sysdeps/ia64/fpu/s_truncl.S: Likewise. * sysdeps/ieee754/dbl-64/doasin.c: Changed copyright notice to reflect IBM donation of math library to FSF * sysdeps/ieee754/dbl-64/dosincos.c: Likewise. * sysdeps/ieee754/dbl-64/e_asin.c: Likewise. * sysdeps/ieee754/dbl-64/e_atan2.c: Likewise. * sysdeps/ieee754/dbl-64/e_exp.c: Likewise. * sysdeps/ieee754/dbl-64/e_log.c: Likewise. * sysdeps/ieee754/dbl-64/e_pow.c: Likewise. * sysdeps/ieee754/dbl-64/e_remainder.c: Likewise. * sysdeps/ieee754/dbl-64/e_sqrt.c: Likewise. * sysdeps/ieee754/dbl-64/halfulp.c: Likewise. * sysdeps/ieee754/dbl-64/mpa.c: Likewise. * sysdeps/ieee754/dbl-64/mpatan.c: Likewise. * sysdeps/ieee754/dbl-64/mpatan2.c: Likewise. * sysdeps/ieee754/dbl-64/mpexp.c: Likewise. * sysdeps/ieee754/dbl-64/mplog.c: Likewise. * sysdeps/ieee754/dbl-64/mpsqrt.c: Likewise. * sysdeps/ieee754/dbl-64/mptan.c: Likewise. * sysdeps/ieee754/dbl-64/s_atan.c: Likewise. * sysdeps/ieee754/dbl-64/s_sin.c: Likewise. * sysdeps/ieee754/dbl-64/s_tan.c: Likewise. * sysdeps/ieee754/dbl-64/sincos32.c: Likewise. * sysdeps/ieee754/dbl-64/slowexp.c: Likewise. * sysdeps/ieee754/dbl-64/slowpow.c: Likewise. * sysdeps/gnu/netinet/udp.h: Added BSD copying permission notice * sysdeps/vax/__longjmp.c: Likewise. * sysdeps/vax/setjmp.c: Likewise. * libio/filedoalloc.c: Fixed BSD copying permission notice to remove advertising clause * sysdeps/vax/htonl.s: Likewise. * sysdeps/vax/htons.s: Likewise. * libio/wfiledoalloc.c: Likewise. * stdlib/random.c: Likewise. * stdlib/random_r.c: Likewise. * sysdeps/mach/sys/reboot.h: Likewise. * inet/getnameinfo.c: Deleted advertising clause from Inner Net License * sysdeps/posix/getaddrinfo.c: Likewise. * sunrpc/des_impl.c: Updated license permission notice to Lesser GPL and corrected pointer to point to the correct license.
286 lines
7.9 KiB
ArmAsm
286 lines
7.9 KiB
ArmAsm
.file "modff.s"
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// Copyright (C) 2000, 2001, Intel Corporation
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// All rights reserved.
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//
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// Contributed 2/2/2000 by John Harrison, Ted Kubaska, Bob Norin, Shane Story,
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// and Ping Tak Peter Tang of the Computational Software Lab, Intel Corporation.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// * The name of Intel Corporation may not be used to endorse or promote
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// products derived from this software without specific prior written
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// permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Intel Corporation is the author of this code, and requests that all
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// problem reports or change requests be submitted to it directly at
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// http://developer.intel.com/opensource.
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//
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// History
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//==============================================================
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// 2/02/00: Initial version
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// 4/04/00: Improved speed, corrected result for NaN input
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// 12/22/00 Fixed so inexact flag is never set, and invalid is not set for
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// qnans nor for inputs larger than 2^63.
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//
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// API
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//==============================================================
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// float modff(float x, float *iptr)
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// break a floating point x number into fraction and an exponent
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//
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// input floating point f8, address in r33
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// output floating point f8 (x fraction), and *iptr (x integral part)
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//
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// OVERVIEW
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//==============================================================
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// NO FRACTIONAL PART: HUGE
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// If
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// for double-extended
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// If the true exponent is greater than or equal 63
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// 1003e ==> 1003e -ffff = 3f = 63(dec)
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// for double
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// If the true exponent is greater than or equal 52
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// 10033 -ffff = 34 = 52(dec)
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// for single
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// If the true exponent is greater than or equal 23
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// 10016 -ffff = 17 = 23(dec)
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// then
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// we are already an integer (p9 true)
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// NO INTEGER PART: SMALL
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// Is f8 exponent less than register bias (that is, is it
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// less than 1). If it is, get the right sign of
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// zero and store this in iptr.
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// CALCULATION: NOT HUGE, NOT SMALL
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// To get the integer part
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// Take the floating-point input and truncate
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// then convert this integer to fp Call it MODF_INTEGER_PART
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// Subtract MODF_INTEGER_PART from MODF_NORM_F8 to get fraction part
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// Then put fraction part in f8
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// put integer part MODF_INTEGER_PART into *iptr
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// Registers used
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//==============================================================
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// predicate registers used:
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// p6 - p13
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// 0xFFFF 0x10016
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// -----------------------+-----------------+-------------
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// SMALL | NORMAL | HUGE
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// p11 --------------->|<----- p12 ----->| <-------------- p9
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// p10 --------------------------------->|
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// p13 --------------------------------------------------->|
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//
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#include "libm_support.h"
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// floating-point registers used:
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MODF_NORM_F8 = f9
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MODF_FRACTION_PART = f10
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MODF_INTEGER_PART = f11
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MODF_INT_INTEGER_PART = f12
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// general registers used
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modf_signexp = r14
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modf_GR_no_frac = r15
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modf_GR_FFFF = r16
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modf_17_ones = r17
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modf_exp = r18
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// r33 = iptr
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.align 32
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.global modff#
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.section .text
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.proc modff#
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.align 32
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// Main path is p9, p11, p8 FALSE and p12 TRUE
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// Assume input is normalized and get signexp
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// Normalize input just in case
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// Form exponent bias
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modff:
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{ .mfi
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getf.exp modf_signexp = f8
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fnorm MODF_NORM_F8 = f8
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addl modf_GR_FFFF = 0xffff, r0
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}
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// Get integer part of input
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// Form exponent mask
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{ .mfi
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nop.m 999
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fcvt.fx.trunc.s1 MODF_INT_INTEGER_PART = f8
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mov modf_17_ones = 0x1ffff ;;
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}
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// Is x nan or inf?
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// qnan snan inf norm unorm 0 -+
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// 1 1 1 0 0 0 11 = 0xe3 NAN_INF
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// Form biased exponent where input only has an integer part
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{ .mfi
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nop.m 999
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fclass.m.unc p6,p13 = f8, 0xe3
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addl modf_GR_no_frac = 0x10016, r0 ;;
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}
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// Mask to get exponent
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// Is x unnorm?
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// qnan snan inf norm unorm 0 -+
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// 0 0 0 0 1 0 11 = 0x0b UNORM
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// Set p13 to indicate calculation path, else p6 if nan or inf
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{ .mfi
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and modf_exp = modf_17_ones, modf_signexp
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fclass.m.unc p8,p0 = f8, 0x0b
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nop.i 999 ;;
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}
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// p11 <== SMALL, no integer part, fraction is everyting
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// p9 <== HUGE, no fraction part, integer is everything
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// p12 <== NORMAL, fraction part and integer part
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{ .mii
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(p13) cmp.lt.unc p11,p10 = modf_exp, modf_GR_FFFF
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nop.i 999
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nop.i 999 ;;
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}
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// Is x inf? p6 if inf, p7 if nan
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{ .mfb
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(p10) cmp.ge.unc p9,p12 = modf_exp, modf_GR_no_frac
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(p6) fclass.m.unc p6,p7 = f8, 0x23
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(p8) br.cond.spnt L(MODF_DENORM) ;;
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}
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L(MODF_COMMON):
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// For HUGE set fraction to signed 0
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{ .mfi
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nop.m 999
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(p9) fmerge.s f8 = f8,f0
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nop.i 999
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}
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// For HUGE set integer part to normalized input
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{ .mfi
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nop.m 999
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(p9) fnorm.s MODF_INTEGER_PART = MODF_NORM_F8
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nop.i 999 ;;
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}
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// For SMALL set fraction to normalized input, integer part to signed 0
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{ .mfi
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nop.m 999
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(p11) fmerge.s MODF_INTEGER_PART = f8,f0
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nop.i 999
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}
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{ .mfi
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nop.m 999
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(p11) fnorm.s f8 = MODF_NORM_F8
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nop.i 999 ;;
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}
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// For NORMAL float the integer part
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{ .mfi
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nop.m 999
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(p12) fcvt.xf MODF_INTEGER_PART = MODF_INT_INTEGER_PART
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nop.i 999 ;;
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}
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// If x inf set integer part to INF, fraction to signed 0
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{ .mfi
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(p6) stfs [r33] = MODF_NORM_F8
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(p6) fmerge.s f8 = f8,f0
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nop.i 999 ;;
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}
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// If x nan set integer and fraction parts to NaN (quietized)
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{ .mfi
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(p7) stfs [r33] = MODF_NORM_F8
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(p7) fmerge.s f8 = MODF_NORM_F8, MODF_NORM_F8
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nop.i 999 ;;
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}
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{ .mmi
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(p9) stfs [r33] = MODF_INTEGER_PART
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nop.m 999
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nop.i 999 ;;
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}
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// For NORMAL compute fraction part
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{ .mfi
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(p11) stfs [r33] = MODF_INTEGER_PART
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(p12) fms.s.s0 f8 = MODF_NORM_F8,f1, MODF_INTEGER_PART
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nop.i 999 ;;
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}
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// For NORMAL test if fraction part is zero; if so append correct sign
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{ .mfi
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nop.m 999
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(p12) fcmp.eq.unc p7,p0 = MODF_NORM_F8, MODF_INTEGER_PART
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nop.i 999 ;;
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}
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{ .mfi
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(p12) stfs [r33] = MODF_INTEGER_PART
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nop.f 999
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nop.i 999 ;;
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}
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// For NORMAL if fraction part is zero append sign of input
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{ .mfb
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nop.m 999
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(p7) fmerge.s f8 = MODF_NORM_F8, f0
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br.ret.sptk b0 ;;
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}
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L(MODF_DENORM):
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// If x unorm get signexp from normalized input
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// If x unorm get integer part from normalized input
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{ .mfi
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getf.exp modf_signexp = MODF_NORM_F8
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fcvt.fx.trunc.s1 MODF_INT_INTEGER_PART = MODF_NORM_F8
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nop.i 999 ;;
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}
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// If x unorm mask to get exponent
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{ .mmi
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and modf_exp = modf_17_ones, modf_signexp ;;
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cmp.lt.unc p11,p10 = modf_exp, modf_GR_FFFF
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nop.i 999 ;;
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}
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{ .mfb
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(p10) cmp.ge.unc p9,p12 = modf_exp, modf_GR_no_frac
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nop.f 999
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br.cond.spnt L(MODF_COMMON) ;;
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}
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.endp modff
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ASM_SIZE_DIRECTIVE(modff)
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