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d5b411854f
A number of functions in the sysdeps/powerpc/powerpc64/ tree don't use or change r2, yet declare a global entry that sets up r2. This patch fixes that problem, and consolidates the ENTRY and EALIGN macros. * sysdeps/powerpc/powerpc64/sysdep.h: Formatting. (NOPS, ENTRY_3): New macros. (ENTRY): Rewrite. (ENTRY_TOCLESS): Define. (EALIGN, EALIGN_W_0, EALIGN_W_1, EALIGN_W_2, EALIGN_W_4, EALIGN_W_5, EALIGN_W_6, EALIGN_W_7, EALIGN_W_8): Delete. * sysdeps/powerpc/powerpc64/a2/memcpy.S: Replace EALIGN with ENTRY. * sysdeps/powerpc/powerpc64/dl-trampoline.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_ceil.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_ceilf.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_floor.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_floorf.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_nearbyint.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_nearbyintf.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_rint.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_rintf.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_round.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_roundf.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_trunc.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_truncf.S: Likewise. * sysdeps/powerpc/powerpc64/memset.S: Likewise. * sysdeps/powerpc/powerpc64/power7/fpu/s_finite.S: Likewise. * sysdeps/powerpc/powerpc64/power7/fpu/s_isinf.S: Likewise. * sysdeps/powerpc/powerpc64/power7/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strstr.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/e_expf.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_cosf.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_sinf.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strcasestr.S: Likewise. * sysdeps/powerpc/powerpc64/addmul_1.S: Use ENTRY_TOCLESS. * sysdeps/powerpc/powerpc64/cell/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_copysign.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_copysignl.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_fabsl.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_llrint.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_llrintf.S: Likewise. * sysdeps/powerpc/powerpc64/lshift.S: Likewise. * sysdeps/powerpc/powerpc64/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/mul_1.S: Likewise. * sysdeps/powerpc/powerpc64/power4/memcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power4/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power4/memset.S: Likewise. * sysdeps/powerpc/powerpc64/power4/strncmp.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_ceil.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_ceilf.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_floor.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_floorf.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_llround.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_round.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_roundf.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_trunc.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_truncf.S: Likewise. * sysdeps/powerpc/powerpc64/power5/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/power6/fpu/s_copysign.S: Likewise. * sysdeps/powerpc/powerpc64/power6/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/power6/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power6/memset.S: Likewise. * sysdeps/powerpc/powerpc64/power6x/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/power6x/fpu/s_llrint.S: Likewise. * sysdeps/powerpc/powerpc64/power6x/fpu/s_llround.S: Likewise. * sysdeps/powerpc/powerpc64/power7/add_n.S: Likewise. * sysdeps/powerpc/powerpc64/power7/memchr.S: Likewise. * sysdeps/powerpc/powerpc64/power7/memcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power7/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power7/memmove.S: Likewise. * sysdeps/powerpc/powerpc64/power7/mempcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power7/memrchr.S: Likewise. * sysdeps/powerpc/powerpc64/power7/memset.S: Likewise. * sysdeps/powerpc/powerpc64/power7/rawmemchr.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strcasecmp.S (strcasecmp_l): Likewise. * sysdeps/powerpc/powerpc64/power7/strchr.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strchrnul.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strlen.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strncmp.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strncpy.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strnlen.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strrchr.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S: Likewise. * sysdeps/powerpc/powerpc64/power8/memcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power8/memset.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strchr.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strlen.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strncmp.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strncpy.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strnlen.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strrchr.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strspn.S: Likewise. * sysdeps/powerpc/powerpc64/power9/strcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power9/strncmp.S: Likewise. * sysdeps/powerpc/powerpc64/strchr.S: Likewise. * sysdeps/powerpc/powerpc64/strcmp.S: Likewise. * sysdeps/powerpc/powerpc64/strlen.S: Likewise. * sysdeps/powerpc/powerpc64/strncmp.S: Likewise. * sysdeps/powerpc/powerpc64/ppc-mcount.S: Store LR earlier. Don't add nop when SHARED. * sysdeps/powerpc/powerpc64/start.S: Fix comment. * sysdeps/powerpc/powerpc64/multiarch/strrchr-power8.S (ENTRY): Don't define. (ENTRY_TOCLESS): Define. * sysdeps/powerpc/powerpc32/sysdep.h (ENTRY_TOCLESS): Define. * sysdeps/powerpc/fpu/s_fma.S: Use ENTRY_TOCLESS. * sysdeps/powerpc/fpu/s_fmaf.S: Likewise.
248 lines
5.7 KiB
ArmAsm
248 lines
5.7 KiB
ArmAsm
/* Optimized strcmp implementation for PowerPC64/POWER8.
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Copyright (C) 2015-2017 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#ifndef STRCMP
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# define STRCMP strcmp
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#endif
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/* Implements the function
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size_t [r3] strcmp (const char *s1 [r3], const char *s2 [r4])
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The implementation uses unaligned doubleword access to avoid specialized
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code paths depending of data alignment. Although recent powerpc64 uses
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64K as default, the page cross handling assumes minimum page size of
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4k. */
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ENTRY_TOCLESS (STRCMP, 4)
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li r0,0
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/* Check if [s1]+16 or [s2]+16 will cross a 4K page boundary using
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the code:
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(((size_t) s1) % PAGE_SIZE > (PAGE_SIZE - ITER_SIZE))
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with PAGE_SIZE being 4096 and ITER_SIZE begin 16. */
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rldicl r7,r3,0,52
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rldicl r9,r4,0,52
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cmpldi cr7,r7,4096-16
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bgt cr7,L(pagecross_check)
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cmpldi cr5,r9,4096-16
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bgt cr5,L(pagecross_check)
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/* For short string up to 16 bytes, load both s1 and s2 using
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unaligned dwords and compare. */
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ld r8,0(r3)
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ld r10,0(r4)
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cmpb r12,r8,r0
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cmpb r11,r8,r10
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orc. r9,r12,r11
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bne cr0,L(different_nocmpb)
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ld r8,8(r3)
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ld r10,8(r4)
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cmpb r12,r8,r0
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cmpb r11,r8,r10
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orc. r9,r12,r11
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bne cr0,L(different_nocmpb)
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addi r7,r3,16
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addi r4,r4,16
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L(align_8b):
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/* Now it has checked for first 16 bytes, align source1 to doubleword
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and adjust source2 address. */
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rldicl r9,r7,0,61 /* source1 alignment to doubleword */
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subf r4,r9,r4 /* Adjust source2 address based on source1
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alignment. */
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rldicr r7,r7,0,60 /* Align source1 to doubleword. */
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/* At this point, source1 alignment is 0 and source2 alignment is
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between 0 and 7. Check is source2 alignment is 0, meaning both
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sources have the same alignment. */
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andi. r9,r4,0x7
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bne cr0,L(loop_diff_align)
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/* If both source1 and source2 are doubleword aligned, there is no
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need for page boundary cross checks. */
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ld r8,0(r7)
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ld r10,0(r4)
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cmpb r12,r8,r0
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cmpb r11,r8,r10
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orc. r9,r12,r11
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bne cr0,L(different_nocmpb)
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.align 4
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L(loop_equal_align):
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ld r8,8(r7)
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ld r10,8(r4)
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cmpb r12,r8,r0
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cmpb r11,r8,r10
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orc. r9,r12,r11
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bne cr0,L(different_nocmpb)
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ld r8,16(r7)
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ld r10,16(r4)
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cmpb r12,r8,r0
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cmpb r11,r8,r10
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orc. r9,r12,r11
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bne cr0,L(different_nocmpb)
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ldu r8,24(r7)
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ldu r10,24(r4)
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cmpb r12,r8,r0
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cmpb r11,r8,r10
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orc. r9,r12,r11
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bne cr0,L(different_nocmpb)
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b L(loop_equal_align)
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/* A zero byte was found in r8 (s1 dword), r9 contains the cmpb
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result and r10 the dword from s2. To code isolate the byte
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up to end (including the '\0'), masking with 0xFF the remaining
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ones:
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#if __LITTLE_ENDIAN__
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(__builtin_ffsl (x) - 1) = counting trailing zero bits
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r9 = (__builtin_ffsl (r9) - 1) + 8;
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r9 = -1UL << r9
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#else
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r9 = __builtin_clzl (r9) + 8;
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r9 = -1UL >> r9
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#endif
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r8 = r8 | r9
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r10 = r10 | r9 */
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#ifdef __LITTLE_ENDIAN__
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nor r9,r9,r9
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L(different_nocmpb):
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neg r3,r9
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and r9,r9,r3
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cntlzd r9,r9
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subfic r9,r9,63
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#else
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not r9,r9
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L(different_nocmpb):
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cntlzd r9,r9
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subfic r9,r9,56
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#endif
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srd r3,r8,r9
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srd r10,r10,r9
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rldicl r10,r10,0,56
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rldicl r3,r3,0,56
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subf r3,r10,r3
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extsw r3,r3
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blr
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.align 4
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L(pagecross_check):
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subfic r9,r9,4096
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subfic r7,r7,4096
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cmpld cr7,r7,r9
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bge cr7,L(pagecross)
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mr r7,r9
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/* If unaligned 16 bytes reads across a 4K page boundary, it uses
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a simple byte a byte comparison until the page alignment for s1
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is reached. */
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L(pagecross):
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add r7,r3,r7
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subf r9,r3,r7
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mtctr r9
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.align 4
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L(pagecross_loop):
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/* Loads a byte from s1 and s2, compare if *s1 is equal to *s2
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and if *s1 is '\0'. */
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lbz r9,0(r3)
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lbz r10,0(r4)
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addi r3,r3,1
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addi r4,r4,1
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cmplw cr7,r9,r10
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cmpdi cr5,r9,r0
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bne cr7,L(pagecross_ne)
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beq cr5,L(pagecross_nullfound)
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bdnz L(pagecross_loop)
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b L(align_8b)
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.align 4
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/* The unaligned read of source2 will cross a 4K page boundary,
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and the different byte or NULL maybe be in the remaining page
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bytes. Since it can not use the unaligned load, the algorithm
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reads and compares 8 bytes to keep source1 doubleword aligned. */
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L(check_source2_byte):
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li r9,8
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mtctr r9
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.align 4
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L(check_source2_byte_loop):
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lbz r9,0(r7)
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lbz r10,0(r4)
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addi r7,r7,1
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addi r4,r4,1
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cmplw cr7,r9,10
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cmpdi r5,r9,0
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bne cr7,L(pagecross_ne)
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beq cr5,L(pagecross_nullfound)
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bdnz L(check_source2_byte_loop)
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/* If source2 is unaligned to doubleword, the code needs to check
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on each interation if the unaligned doubleword access will cross
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a 4k page boundary. */
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.align 5
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L(loop_unaligned):
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ld r8,0(r7)
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ld r10,0(r4)
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cmpb r12,r8,r0
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cmpb r11,r8,r10
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orc. r9,r12,r11
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bne cr0,L(different_nocmpb)
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addi r7,r7,8
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addi r4,r4,8
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L(loop_diff_align):
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/* Check if [src2]+8 cross a 4k page boundary:
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srcin2 % PAGE_SIZE > (PAGE_SIZE - 8)
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with PAGE_SIZE being 4096. */
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rldicl r9,r4,0,52
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cmpldi cr7,r9,4088
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ble cr7,L(loop_unaligned)
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b L(check_source2_byte)
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.align 4
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L(pagecross_ne):
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extsw r3,r9
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mr r9,r10
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L(pagecross_retdiff):
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subf r9,r9,r3
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extsw r3,r9
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blr
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.align 4
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L(pagecross_nullfound):
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li r3,0
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b L(pagecross_retdiff)
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END (STRCMP)
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libc_hidden_builtin_def (strcmp)
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