mirror of
https://sourceware.org/git/glibc.git
synced 2024-11-27 07:20:11 +00:00
4372980f58
I've moved the TILE-Gx and TILEPro ports to the main sysdeps hierarchy,
along with the linux-generic ports infrastructure. Beyond the README
update, the move was just
git mv ports/sysdeps/tile sysdeps/tile
git mv ports/sysdeps/unix/sysv/linux/tile \
sysdeps/unix/sysv/linux/tile
git mv ports/sysdeps/unix/sysv/linux/generic \
sysdeps/unix/sysv/linux/generic
I updated the relevant ChangeLogs along the lines of the ARM move
in commit c6bfe5c4d7 and tested the 64-bit tilegx build to confirm that
there were no changes in "objdump -dr" output in the shared objects.
398 lines
14 KiB
ArmAsm
398 lines
14 KiB
ArmAsm
/* Copyright (C) 2011-2014 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Chris Metcalf <cmetcalf@tilera.com>, 2011.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#include <arch/chip.h>
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#include <sysdep.h>
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.text
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ENTRY (__memcpy)
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FEEDBACK_ENTER(__memcpy)
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/* r0 is the dest, r1 is the source, r2 is the size. */
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/* Save aside original dest so we can return it at the end. */
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{ sw sp, lr; move r23, r0; or r4, r0, r1 }
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cfi_offset (lr, 0)
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/* Check for an empty size. */
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{ bz r2, .Ldone; andi r4, r4, 3 }
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/* Check for an unaligned source or dest. */
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{ bnz r4, .Lcopy_unaligned_maybe_many; addli r4, r2, -256 }
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.Lcheck_aligned_copy_size:
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/* If we are copying < 256 bytes, branch to simple case. */
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{ blzt r4, .Lcopy_8_check; slti_u r8, r2, 8 }
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/* Copying >= 256 bytes, so jump to complex prefetching loop. */
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{ andi r6, r1, 63; j .Lcopy_many }
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/* Aligned 4 byte at a time copy loop. */
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.Lcopy_8_loop:
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/* Copy two words at a time to hide load latency. */
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{ lw r3, r1; addi r1, r1, 4; slti_u r8, r2, 16 }
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{ lw r4, r1; addi r1, r1, 4 }
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{ sw r0, r3; addi r0, r0, 4; addi r2, r2, -4 }
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{ sw r0, r4; addi r0, r0, 4; addi r2, r2, -4 }
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.Lcopy_8_check:
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{ bzt r8, .Lcopy_8_loop; slti_u r4, r2, 4 }
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/* Copy odd leftover word, if any. */
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{ bnzt r4, .Lcheck_odd_stragglers }
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{ lw r3, r1; addi r1, r1, 4 }
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{ sw r0, r3; addi r0, r0, 4; addi r2, r2, -4 }
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.Lcheck_odd_stragglers:
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{ bnz r2, .Lcopy_unaligned_few }
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.Ldone:
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{ move r0, r23; jrp lr }
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/* Prefetching multiple cache line copy handler (for large transfers). */
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/* Copy words until r1 is cache-line-aligned. */
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.Lalign_loop:
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{ lw r3, r1; addi r1, r1, 4 }
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{ andi r6, r1, 63 }
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{ sw r0, r3; addi r0, r0, 4; addi r2, r2, -4 }
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.Lcopy_many:
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{ bnzt r6, .Lalign_loop; addi r9, r0, 63 }
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{ addi r3, r1, 60; andi r9, r9, -64 }
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/* No need to prefetch dst, we'll just do the wh64
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right before we copy a line. */
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{ lw r5, r3; addi r3, r3, 64; movei r4, 1 }
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/* Intentionally stall for a few cycles to leave L2 cache alone. */
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{ bnzt zero, .; move r27, lr }
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{ lw r6, r3; addi r3, r3, 64 }
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/* Intentionally stall for a few cycles to leave L2 cache alone. */
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{ bnzt zero, . }
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{ lw r7, r3; addi r3, r3, 64 }
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/* Intentionally stall for a few cycles to leave L2 cache alone. */
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{ bz zero, .Lbig_loop2 }
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/* On entry to this loop:
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- r0 points to the start of dst line 0
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- r1 points to start of src line 0
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- r2 >= (256 - 60), only the first time the loop trips.
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- r3 contains r1 + 128 + 60 [pointer to end of source line 2]
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This is our prefetch address. When we get near the end
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rather than prefetching off the end this is changed to point
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to some "safe" recently loaded address.
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- r5 contains *(r1 + 60) [i.e. last word of source line 0]
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- r6 contains *(r1 + 64 + 60) [i.e. last word of source line 1]
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- r9 contains ((r0 + 63) & -64)
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[start of next dst cache line.] */
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.Lbig_loop:
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{ jal .Lcopy_line2; add r15, r1, r2 }
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.Lbig_loop2:
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/* Copy line 0, first stalling until r5 is ready. */
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{ move r12, r5; lw r16, r1 }
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{ bz r4, .Lcopy_8_check; slti_u r8, r2, 8 }
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/* Prefetch several lines ahead. */
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{ lw r5, r3; addi r3, r3, 64 }
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{ jal .Lcopy_line }
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/* Copy line 1, first stalling until r6 is ready. */
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{ move r12, r6; lw r16, r1 }
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{ bz r4, .Lcopy_8_check; slti_u r8, r2, 8 }
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/* Prefetch several lines ahead. */
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{ lw r6, r3; addi r3, r3, 64 }
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{ jal .Lcopy_line }
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/* Copy line 2, first stalling until r7 is ready. */
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{ move r12, r7; lw r16, r1 }
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{ bz r4, .Lcopy_8_check; slti_u r8, r2, 8 }
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/* Prefetch several lines ahead. */
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{ lw r7, r3; addi r3, r3, 64 }
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/* Use up a caches-busy cycle by jumping back to the top of the
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loop. Might as well get it out of the way now. */
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{ j .Lbig_loop }
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/* On entry:
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- r0 points to the destination line.
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- r1 points to the source line.
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- r3 is the next prefetch address.
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- r9 holds the last address used for wh64.
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- r12 = WORD_15
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- r16 = WORD_0.
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- r17 == r1 + 16.
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- r27 holds saved lr to restore.
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On exit:
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- r0 is incremented by 64.
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- r1 is incremented by 64, unless that would point to a word
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beyond the end of the source array, in which case it is redirected
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to point to an arbitrary word already in the cache.
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- r2 is decremented by 64.
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- r3 is unchanged, unless it points to a word beyond the
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end of the source array, in which case it is redirected
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to point to an arbitrary word already in the cache.
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Redirecting is OK since if we are that close to the end
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of the array we will not come back to this subroutine
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and use the contents of the prefetched address.
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- r4 is nonzero iff r2 >= 64.
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- r9 is incremented by 64, unless it points beyond the
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end of the last full destination cache line, in which
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case it is redirected to a "safe address" that can be
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clobbered (sp - 64)
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- lr contains the value in r27. */
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/* r26 unused */
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.Lcopy_line:
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/* TODO: when r3 goes past the end, we would like to redirect it
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to prefetch the last partial cache line (if any) just once, for the
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benefit of the final cleanup loop. But we don't want to
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prefetch that line more than once, or subsequent prefetches
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will go into the RTF. But then .Lbig_loop should unconditionally
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branch to top of loop to execute final prefetch, and its
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nop should become a conditional branch. */
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/* We need two non-memory cycles here to cover the resources
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used by the loads initiated by the caller. */
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{ add r15, r1, r2 }
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.Lcopy_line2:
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{ slt_u r13, r3, r15; addi r17, r1, 16 }
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/* NOTE: this will stall for one cycle as L1 is busy. */
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/* Fill second L1D line. */
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{ lw r17, r17; addi r1, r1, 48; mvz r3, r13, r1 } /* r17 = WORD_4 */
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/* Prepare destination line for writing. */
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{ wh64 r9; addi r9, r9, 64 }
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/* Load seven words that are L1D hits to cover wh64 L2 usage. */
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/* Load the three remaining words from the last L1D line, which
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we know has already filled the L1D. */
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{ lw r4, r1; addi r1, r1, 4; addi r20, r1, 16 } /* r4 = WORD_12 */
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{ lw r8, r1; addi r1, r1, 4; slt_u r13, r20, r15 }/* r8 = WORD_13 */
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{ lw r11, r1; addi r1, r1, -52; mvz r20, r13, r1 } /* r11 = WORD_14 */
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/* Load the three remaining words from the first L1D line, first
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stalling until it has filled by "looking at" r16. */
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{ lw r13, r1; addi r1, r1, 4; move zero, r16 } /* r13 = WORD_1 */
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{ lw r14, r1; addi r1, r1, 4 } /* r14 = WORD_2 */
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{ lw r15, r1; addi r1, r1, 8; addi r10, r0, 60 } /* r15 = WORD_3 */
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/* Load second word from the second L1D line, first
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stalling until it has filled by "looking at" r17. */
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{ lw r19, r1; addi r1, r1, 4; move zero, r17 } /* r19 = WORD_5 */
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/* Store last word to the destination line, potentially dirtying it
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for the first time, which keeps the L2 busy for two cycles. */
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{ sw r10, r12 } /* store(WORD_15) */
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/* Use two L1D hits to cover the sw L2 access above. */
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{ lw r10, r1; addi r1, r1, 4 } /* r10 = WORD_6 */
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{ lw r12, r1; addi r1, r1, 4 } /* r12 = WORD_7 */
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/* Fill third L1D line. */
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{ lw r18, r1; addi r1, r1, 4 } /* r18 = WORD_8 */
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/* Store first L1D line. */
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{ sw r0, r16; addi r0, r0, 4; add r16, r0, r2 } /* store(WORD_0) */
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{ sw r0, r13; addi r0, r0, 4; andi r16, r16, -64 } /* store(WORD_1) */
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{ sw r0, r14; addi r0, r0, 4; slt_u r16, r9, r16 } /* store(WORD_2) */
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{ sw r0, r15; addi r0, r0, 4; addi r13, sp, -64 } /* store(WORD_3) */
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/* Store second L1D line. */
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{ sw r0, r17; addi r0, r0, 4; mvz r9, r16, r13 }/* store(WORD_4) */
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{ sw r0, r19; addi r0, r0, 4 } /* store(WORD_5) */
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{ sw r0, r10; addi r0, r0, 4 } /* store(WORD_6) */
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{ sw r0, r12; addi r0, r0, 4 } /* store(WORD_7) */
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{ lw r13, r1; addi r1, r1, 4; move zero, r18 } /* r13 = WORD_9 */
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{ lw r14, r1; addi r1, r1, 4 } /* r14 = WORD_10 */
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{ lw r15, r1; move r1, r20 } /* r15 = WORD_11 */
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/* Store third L1D line. */
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{ sw r0, r18; addi r0, r0, 4 } /* store(WORD_8) */
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{ sw r0, r13; addi r0, r0, 4 } /* store(WORD_9) */
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{ sw r0, r14; addi r0, r0, 4 } /* store(WORD_10) */
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{ sw r0, r15; addi r0, r0, 4 } /* store(WORD_11) */
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/* Store rest of fourth L1D line. */
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{ sw r0, r4; addi r0, r0, 4 } /* store(WORD_12) */
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{
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sw r0, r8 /* store(WORD_13) */
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addi r0, r0, 4
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/* Will r2 be > 64 after we subtract 64 below? */
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shri r4, r2, 7
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}
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{
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sw r0, r11 /* store(WORD_14) */
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addi r0, r0, 8
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/* Record 64 bytes successfully copied. */
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addi r2, r2, -64
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}
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{ jrp lr; move lr, r27 }
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/* Convey to the backtrace library that the stack frame is
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size zero, and the real return address is on the stack
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rather than in 'lr'. */
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{ info 8 }
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.align 64
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.Lcopy_unaligned_maybe_many:
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/* Skip the setup overhead if we aren't copying many bytes. */
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{ slti_u r8, r2, 20; sub r4, zero, r0 }
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{ bnzt r8, .Lcopy_unaligned_few; andi r4, r4, 3 }
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{ bz r4, .Ldest_is_word_aligned; add r18, r1, r2 }
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/* Unaligned 4 byte at a time copy handler. */
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/* Copy single bytes until r0 == 0 mod 4, so we can store words. */
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.Lalign_dest_loop:
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{ lb_u r3, r1; addi r1, r1, 1; addi r4, r4, -1 }
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{ sb r0, r3; addi r0, r0, 1; addi r2, r2, -1 }
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{ bnzt r4, .Lalign_dest_loop; andi r3, r1, 3 }
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/* If source and dest are now *both* aligned, do an aligned copy. */
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{ bz r3, .Lcheck_aligned_copy_size; addli r4, r2, -256 }
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.Ldest_is_word_aligned:
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{ andi r8, r0, 63; lwadd_na r6, r1, 4}
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{ slti_u r9, r2, 64; bz r8, .Ldest_is_L2_line_aligned }
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/* This copies unaligned words until either there are fewer
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than 4 bytes left to copy, or until the destination pointer
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is cache-aligned, whichever comes first.
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On entry:
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- r0 is the next store address.
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- r1 points 4 bytes past the load address corresponding to r0.
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- r2 >= 4
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- r6 is the next aligned word loaded. */
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.Lcopy_unaligned_src_words:
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{ lwadd_na r7, r1, 4; slti_u r8, r2, 4 + 4 }
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/* stall */
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{ dword_align r6, r7, r1; slti_u r9, r2, 64 + 4 }
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{ swadd r0, r6, 4; addi r2, r2, -4 }
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{ bnz r8, .Lcleanup_unaligned_words; andi r8, r0, 63 }
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{ bnzt r8, .Lcopy_unaligned_src_words; move r6, r7 }
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/* On entry:
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- r0 is the next store address.
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- r1 points 4 bytes past the load address corresponding to r0.
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- r2 >= 4 (# of bytes left to store).
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- r6 is the next aligned src word value.
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- r9 = (r2 < 64U).
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- r18 points one byte past the end of source memory. */
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.Ldest_is_L2_line_aligned:
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{
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/* Not a full cache line remains. */
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bnz r9, .Lcleanup_unaligned_words
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move r7, r6
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}
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/* r2 >= 64 */
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/* Kick off two prefetches, but don't go past the end. */
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{ addi r3, r1, 63 - 4; addi r8, r1, 64 + 63 - 4 }
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{ prefetch r3; move r3, r8; slt_u r8, r8, r18 }
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{ mvz r3, r8, r1; addi r8, r3, 64 }
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{ prefetch r3; move r3, r8; slt_u r8, r8, r18 }
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{ mvz r3, r8, r1; movei r17, 0 }
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.Lcopy_unaligned_line:
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/* Prefetch another line. */
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{ prefetch r3; addi r15, r1, 60; addi r3, r3, 64 }
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/* Fire off a load of the last word we are about to copy. */
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{ lw_na r15, r15; slt_u r8, r3, r18 }
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{ mvz r3, r8, r1; wh64 r0 }
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/* This loop runs twice.
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On entry:
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- r17 is even before the first iteration, and odd before
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the second. It is incremented inside the loop. Encountering
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an even value at the end of the loop makes it stop. */
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.Lcopy_half_an_unaligned_line:
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{
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/* Stall until the last byte is ready. In the steady state this
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guarantees all words to load below will be in the L2 cache, which
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avoids shunting the loads to the RTF. */
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move zero, r15
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lwadd_na r7, r1, 16
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}
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{ lwadd_na r11, r1, 12 }
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{ lwadd_na r14, r1, -24 }
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{ lwadd_na r8, r1, 4 }
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{ lwadd_na r9, r1, 4 }
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{
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lwadd_na r10, r1, 8
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/* r16 = (r2 < 64), after we subtract 32 from r2 below. */
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slti_u r16, r2, 64 + 32
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}
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{ lwadd_na r12, r1, 4; addi r17, r17, 1 }
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{ lwadd_na r13, r1, 8; dword_align r6, r7, r1 }
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{ swadd r0, r6, 4; dword_align r7, r8, r1 }
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{ swadd r0, r7, 4; dword_align r8, r9, r1 }
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{ swadd r0, r8, 4; dword_align r9, r10, r1 }
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{ swadd r0, r9, 4; dword_align r10, r11, r1 }
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{ swadd r0, r10, 4; dword_align r11, r12, r1 }
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{ swadd r0, r11, 4; dword_align r12, r13, r1 }
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{ swadd r0, r12, 4; dword_align r13, r14, r1 }
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{ swadd r0, r13, 4; addi r2, r2, -32 }
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{ move r6, r14; bbst r17, .Lcopy_half_an_unaligned_line }
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{ bzt r16, .Lcopy_unaligned_line; move r7, r6 }
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/* On entry:
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- r0 is the next store address.
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- r1 points 4 bytes past the load address corresponding to r0.
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- r2 >= 0 (# of bytes left to store).
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- r7 is the next aligned src word value. */
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.Lcleanup_unaligned_words:
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/* Handle any trailing bytes. */
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{ bz r2, .Lcopy_unaligned_done; slti_u r8, r2, 4 }
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{ bzt r8, .Lcopy_unaligned_src_words; move r6, r7 }
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/* Move r1 back to the point where it corresponds to r0. */
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{ addi r1, r1, -4 }
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/* Fall through */
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/* 1 byte at a time copy handler. */
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.Lcopy_unaligned_few:
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{ lb_u r3, r1; addi r1, r1, 1 }
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{ sb r0, r3; addi r0, r0, 1; addi r2, r2, -1 }
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{ bnzt r2, .Lcopy_unaligned_few }
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|
|
.Lcopy_unaligned_done:
|
|
|
|
{ move r0, r23; jrp lr }
|
|
|
|
END (__memcpy)
|
|
|
|
weak_alias (__memcpy, memcpy)
|
|
libc_hidden_builtin_def (memcpy)
|