mirror of
https://sourceware.org/git/glibc.git
synced 2024-12-27 13:10:29 +00:00
aeb25823d8
2002-06-05 Brian Youmans <3diff@gnu.org> * sysdeps/ia64/fpu/e_acos.S: Added text of Intel license. * sysdeps/ia64/fpu/e_acosf.S: Likewise. * sysdeps/ia64/fpu/e_acosl.S: Likewise. * sysdeps/ia64/fpu/e_asin.S: Likewise. * sysdeps/ia64/fpu/e_asinf.S: Likewise. * sysdeps/ia64/fpu/e_asinl.S: Likewise. * sysdeps/ia64/fpu/e_atan2.S: Likewise. * sysdeps/ia64/fpu/e_atan2f.S: Likewise. * sysdeps/ia64/fpu/e_cosh.S: Likewise. * sysdeps/ia64/fpu/e_coshf.S: Likewise. * sysdeps/ia64/fpu/e_coshl.S: Likewise. * sysdeps/ia64/fpu/e_exp.S: Likewise. * sysdeps/ia64/fpu/e_expf.S: Likewise. * sysdeps/ia64/fpu/e_fmod.S: Likewise. * sysdeps/ia64/fpu/e_fmodf.S: Likewise. * sysdeps/ia64/fpu/e_fmodl.S: Likewise. * sysdeps/ia64/fpu/e_hypot.S: Likewise. * sysdeps/ia64/fpu/e_hypotf.S: Likewise. * sysdeps/ia64/fpu/e_hypotl.S: Likewise. * sysdeps/ia64/fpu/e_log.S: Likewise. * sysdeps/ia64/fpu/e_logf.S: Likewise. * sysdeps/ia64/fpu/e_pow.S: Likewise. * sysdeps/ia64/fpu/e_powf.S: Likewise. * sysdeps/ia64/fpu/e_powl.S: Likewise. * sysdeps/ia64/fpu/e_remainder.S: Likewise. * sysdeps/ia64/fpu/e_remainderf.S: Likewise. * sysdeps/ia64/fpu/e_remainderl.S: Likewise. * sysdeps/ia64/fpu/e_scalb.S: Likewise. * sysdeps/ia64/fpu/e_scalbf.S: Likewise. * sysdeps/ia64/fpu/e_scalbl.S: Likewise. * sysdeps/ia64/fpu/e_sinh.S: Likewise. * sysdeps/ia64/fpu/e_sinhf.S: Likewise. * sysdeps/ia64/fpu/e_sinhl.S: Likewise. * sysdeps/ia64/fpu/e_sqrt.S: Likewise. * sysdeps/ia64/fpu/e_sqrtf.S: Likewise. * sysdeps/ia64/fpu/e_sqrtl.S: Likewise. * sysdeps/ia64/fpu/libm_atan2_req.S: Likewise. * sysdeps/ia64/fpu/libm_error.c: Likewise. * sysdeps/ia64/fpu/libm_frexp4.S: Likewise. * sysdeps/ia64/fpu/libm_frexp4f.S: Likewise. * sysdeps/ia64/fpu/s_frexpl.c: Likewise. * sysdeps/ia64/fpu/s_ilogb.S: Likewise. * sysdeps/ia64/fpu/s_ilogbf.S: Likewise. * sysdeps/ia64/fpu/s_ilogbl.S: Likewise. * sysdeps/ia64/fpu/s_ldexp.S: Likewise. * sysdeps/ia64/fpu/s_ldexpf.S: Likewise. * sysdeps/ia64/fpu/s_ldexpl.S: Likewise. * sysdeps/ia64/fpu/s_log1p.S: Likewise. * sysdeps/ia64/fpu/s_log1pf.S: Likewise. * sysdeps/ia64/fpu/s_log1pl.S: Likewise. * sysdeps/ia64/fpu/s_logb.S: Likewise. * sysdeps/ia64/fpu/s_logbf.S: Likewise. * sysdeps/ia64/fpu/s_logbl.S: Likewise. * sysdeps/ia64/fpu/s_modf.S: Likewise. * sysdeps/ia64/fpu/s_modff.S: Likewise. * sysdeps/ia64/fpu/s_modfl.S: Likewise. * sysdeps/ia64/fpu/s_nearbyint.S: Likewise. * sysdeps/ia64/fpu/s_nearbyintf.S: Likewise. * sysdeps/ia64/fpu/s_nearbyintl.S: Likewise. * sysdeps/ia64/fpu/s_rint.S: Likewise. * sysdeps/ia64/fpu/s_rintf.S: Likewise. * sysdeps/ia64/fpu/s_rintl.S: Likewise. * sysdeps/ia64/fpu/s_round.S: Likewise. * sysdeps/ia64/fpu/s_roundf.S: Likewise. * sysdeps/ia64/fpu/s_roundl.S: Likewise. * sysdeps/ia64/fpu/s_scalbn.S: Likewise. * sysdeps/ia64/fpu/s_scalbnf.S: Likewise. * sysdeps/ia64/fpu/s_scalbnl.S: Likewise. * sysdeps/ia64/fpu/s_significand.S: Likewise. * sysdeps/ia64/fpu/s_significandf.S: Likewise. * sysdeps/ia64/fpu/s_significandl.S: Likewise. * sysdeps/ia64/fpu/s_tan.S: Likewise. * sysdeps/ia64/fpu/s_tanf.S: Likewise. * sysdeps/ia64/fpu/s_tanl.S: Likewise. * sysdeps/ia64/fpu/s_trunc.S: Likewise. * sysdeps/ia64/fpu/s_truncf.S: Likewise. * sysdeps/ia64/fpu/s_truncl.S: Likewise. * sysdeps/ieee754/dbl-64/doasin.c: Changed copyright notice to reflect IBM donation of math library to FSF * sysdeps/ieee754/dbl-64/dosincos.c: Likewise. * sysdeps/ieee754/dbl-64/e_asin.c: Likewise. * sysdeps/ieee754/dbl-64/e_atan2.c: Likewise. * sysdeps/ieee754/dbl-64/e_exp.c: Likewise. * sysdeps/ieee754/dbl-64/e_log.c: Likewise. * sysdeps/ieee754/dbl-64/e_pow.c: Likewise. * sysdeps/ieee754/dbl-64/e_remainder.c: Likewise. * sysdeps/ieee754/dbl-64/e_sqrt.c: Likewise. * sysdeps/ieee754/dbl-64/halfulp.c: Likewise. * sysdeps/ieee754/dbl-64/mpa.c: Likewise. * sysdeps/ieee754/dbl-64/mpatan.c: Likewise. * sysdeps/ieee754/dbl-64/mpatan2.c: Likewise. * sysdeps/ieee754/dbl-64/mpexp.c: Likewise. * sysdeps/ieee754/dbl-64/mplog.c: Likewise. * sysdeps/ieee754/dbl-64/mpsqrt.c: Likewise. * sysdeps/ieee754/dbl-64/mptan.c: Likewise. * sysdeps/ieee754/dbl-64/s_atan.c: Likewise. * sysdeps/ieee754/dbl-64/s_sin.c: Likewise. * sysdeps/ieee754/dbl-64/s_tan.c: Likewise. * sysdeps/ieee754/dbl-64/sincos32.c: Likewise. * sysdeps/ieee754/dbl-64/slowexp.c: Likewise. * sysdeps/ieee754/dbl-64/slowpow.c: Likewise. * sysdeps/gnu/netinet/udp.h: Added BSD copying permission notice * sysdeps/vax/__longjmp.c: Likewise. * sysdeps/vax/setjmp.c: Likewise. * libio/filedoalloc.c: Fixed BSD copying permission notice to remove advertising clause * sysdeps/vax/htonl.s: Likewise. * sysdeps/vax/htons.s: Likewise. * libio/wfiledoalloc.c: Likewise. * stdlib/random.c: Likewise. * stdlib/random_r.c: Likewise. * sysdeps/mach/sys/reboot.h: Likewise. * inet/getnameinfo.c: Deleted advertising clause from Inner Net License * sysdeps/posix/getaddrinfo.c: Likewise. * sunrpc/des_impl.c: Updated license permission notice to Lesser GPL and corrected pointer to point to the correct license.
295 lines
7.6 KiB
ArmAsm
295 lines
7.6 KiB
ArmAsm
.file "sqrtl.s"
|
|
|
|
// Copyright (C) 2000, 2001, Intel Corporation
|
|
// All rights reserved.
|
|
//
|
|
// Contributed 2/2/2000 by John Harrison, Ted Kubaska, Bob Norin, Shane Story,
|
|
// and Ping Tak Peter Tang of the Computational Software Lab, Intel Corporation.
|
|
//
|
|
// Redistribution and use in source and binary forms, with or without
|
|
// modification, are permitted provided that the following conditions are
|
|
// met:
|
|
//
|
|
// * Redistributions of source code must retain the above copyright
|
|
// notice, this list of conditions and the following disclaimer.
|
|
//
|
|
// * Redistributions in binary form must reproduce the above copyright
|
|
// notice, this list of conditions and the following disclaimer in the
|
|
// documentation and/or other materials provided with the distribution.
|
|
//
|
|
// * The name of Intel Corporation may not be used to endorse or promote
|
|
// products derived from this software without specific prior written
|
|
// permission.
|
|
//
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
|
|
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
|
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
|
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
|
|
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
|
|
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
//
|
|
// Intel Corporation is the author of this code, and requests that all
|
|
// problem reports or change requests be submitted to it directly at
|
|
// http://developer.intel.com/opensource.
|
|
//
|
|
// ********************************************************************
|
|
//
|
|
// History:
|
|
// 2/02/00 (hand-optimized)
|
|
// 4/04/00 Unwind support added
|
|
// 8/15/00 Bundle added after call to __libm_error_support to properly
|
|
// set [the previously overwritten] GR_Parameter_RESULT.
|
|
//
|
|
// ********************************************************************
|
|
//
|
|
// Function: Combined sqrtl(x), where
|
|
// _
|
|
// sqrtl(x) = |x, for double-extended precision x values
|
|
//
|
|
// ********************************************************************
|
|
//
|
|
// Resources Used:
|
|
//
|
|
// Floating-Point Registers: f8 (Input and Return Value)
|
|
// f7 -f14
|
|
//
|
|
// General Purpose Registers:
|
|
// r32-r36 (Locals)
|
|
// r37-r40 (Used to pass arguments to error handling routine)
|
|
//
|
|
// Predicate Registers: p6, p7, p8
|
|
//
|
|
// ********************************************************************
|
|
//
|
|
// IEEE Special Conditions:
|
|
//
|
|
// All faults and exceptions should be raised correctly.
|
|
// sqrtl(QNaN) = QNaN
|
|
// sqrtl(SNaN) = QNaN
|
|
// sqrtl(+/-0) = +/-0
|
|
// sqrtl(negative) = QNaN and error handling is called
|
|
//
|
|
// ********************************************************************
|
|
//
|
|
// Implementation:
|
|
//
|
|
// Modified Newton-Raphson Algorithm
|
|
//
|
|
// ********************************************************************
|
|
|
|
#include "libm_support.h"
|
|
|
|
GR_SAVE_PFS = r33
|
|
GR_SAVE_B0 = r34
|
|
GR_SAVE_GP = r35
|
|
GR_Parameter_X = r37
|
|
GR_Parameter_Y = r38
|
|
GR_Parameter_RESULT = r39
|
|
GR_Parameter_TAG = r40
|
|
|
|
FR_X = f15
|
|
FR_Y = f0
|
|
FR_RESULT = f8
|
|
|
|
.section .text
|
|
.proc sqrtl#
|
|
.global sqrtl#
|
|
.align 64
|
|
|
|
sqrtl:
|
|
#ifdef _LIBC
|
|
.global __sqrtl
|
|
.type __sqrtl,@function
|
|
__sqrtl:
|
|
.global __ieee754_sqrtl
|
|
.type __ieee754_sqrtl,@function
|
|
__ieee754_sqrtl:
|
|
#endif
|
|
{ .mlx
|
|
alloc r32= ar.pfs,0,5,4,0
|
|
// exponent of +1/2 in r2
|
|
movl r2 = 0x0fffe;;
|
|
} { .mfi
|
|
// +1/2 in f10
|
|
setf.exp f12 = r2
|
|
// Step (1)
|
|
// y0 = 1/sqrt(a) in f7
|
|
frsqrta.s0 f7,p6=f8
|
|
nop.i 0;;
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (2)
|
|
// H0 = +1/2 * y0 in f9
|
|
(p6) fma.s1 f9=f12,f7,f0
|
|
nop.i 0
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (3)
|
|
// S0 = a * y0 in f7
|
|
(p6) fma.s1 f7=f8,f7,f0
|
|
nop.i 0;;
|
|
} { .mfi
|
|
nop.m 0
|
|
// Make copy input x
|
|
mov f13=f8
|
|
nop.i 0
|
|
} { .mfi
|
|
nop.m 0
|
|
fclass.m.unc p7,p8 = f8,0x3A
|
|
nop.i 0;;
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (4)
|
|
// d0 = 1/2 - S0 * H0 in f10
|
|
(p6) fnma.s1 f10=f7,f9,f12
|
|
nop.i 0;;
|
|
}
|
|
{ .mfi
|
|
nop.m 0
|
|
(p0) mov f15=f8
|
|
nop.i 0;;
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (5)
|
|
// H1 = H0 + d0 * H0 in f9
|
|
(p6) fma.s1 f9=f10,f9,f9
|
|
nop.i 0
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (6)
|
|
// S1 = S0 + d0 * S0 in f7
|
|
(p6) fma.s1 f7=f10,f7,f7
|
|
nop.i 0;;
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (7)
|
|
// d1 = 1/2 - S1 * H1 in f10
|
|
(p6) fnma.s1 f10=f7,f9,f12
|
|
nop.i 0;;
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (8)
|
|
// H2 = H1 + d1 * H1 in f9
|
|
(p6) fma.s1 f9=f10,f9,f9
|
|
nop.i 0
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (9)
|
|
// S2 = S1 + d1 * S1 in f7
|
|
(p6) fma.s1 f7=f10,f7,f7
|
|
nop.i 0;;
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (10)
|
|
// d2 = 1/2 - S2 * H2 in f10
|
|
(p6) fnma.s1 f10=f7,f9,f12
|
|
nop.i 0
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (11)
|
|
// e2 = a - S2 * S2 in f12
|
|
(p6) fnma.s1 f12=f7,f7,f8
|
|
nop.i 0;;
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (12)
|
|
// S3 = S2 + d2 * S2 in f7
|
|
(p6) fma.s1 f7=f12,f9,f7
|
|
nop.i 0
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (13)
|
|
// H3 = H2 + d2 * H2 in f9
|
|
(p6) fma.s1 f9=f10,f9,f9
|
|
nop.i 0;;
|
|
} { .mfi
|
|
nop.m 0
|
|
// Step (14)
|
|
// e3 = a - S3 * S3 in f12
|
|
(p6) fnma.s1 f12=f7,f7,f8
|
|
nop.i 0;;
|
|
} { .mfb
|
|
nop.m 0
|
|
// Step (15)
|
|
// S = S3 + e3 * H3 in f7
|
|
(p6) fma.s0 f8=f12,f9,f7
|
|
(p6) br.ret.sptk b0 ;;
|
|
}
|
|
{ .mfb
|
|
(p0) mov GR_Parameter_TAG = 48
|
|
(p0) mov f8 = f7
|
|
(p8) br.ret.sptk b0 ;;
|
|
}
|
|
//
|
|
// This branch includes all those special values that are not negative,
|
|
// with the result equal to frcpa(x)
|
|
//
|
|
|
|
|
|
// END DOUBLE EXTENDED PRECISION MINIMUM LATENCY SQUARE ROOT ALGORITHM
|
|
.endp sqrtl#
|
|
ASM_SIZE_DIRECTIVE(sqrtl)
|
|
#ifdef _LIBC
|
|
ASM_SIZE_DIRECTIVE(__sqrtl)
|
|
ASM_SIZE_DIRECTIVE(__ieee754_sqrtl)
|
|
#endif
|
|
|
|
.proc __libm_error_region
|
|
__libm_error_region:
|
|
.prologue
|
|
{ .mfi
|
|
add GR_Parameter_Y=-32,sp // Parameter 2 value
|
|
nop.f 0
|
|
.save ar.pfs,GR_SAVE_PFS
|
|
mov GR_SAVE_PFS=ar.pfs // Save ar.pfs
|
|
}
|
|
{ .mfi
|
|
.fframe 64
|
|
add sp=-64,sp // Create new stack
|
|
nop.f 0
|
|
mov GR_SAVE_GP=gp // Save gp
|
|
};;
|
|
{ .mmi
|
|
stfe [GR_Parameter_Y] = FR_Y,16 // Save Parameter 2 on stack
|
|
add GR_Parameter_X = 16,sp // Parameter 1 address
|
|
.save b0, GR_SAVE_B0
|
|
mov GR_SAVE_B0=b0 // Save b0
|
|
};;
|
|
.body
|
|
{ .mib
|
|
stfe [GR_Parameter_X] = FR_X // Store Parameter 1 on stack
|
|
add GR_Parameter_RESULT = 0,GR_Parameter_Y
|
|
nop.b 0 // Parameter 3 address
|
|
}
|
|
{ .mib
|
|
stfe [GR_Parameter_Y] = FR_RESULT // Store Parameter 3 on stack
|
|
add GR_Parameter_Y = -16,GR_Parameter_Y
|
|
br.call.sptk b0=__libm_error_support# // Call error handling function
|
|
};;
|
|
{ .mmi
|
|
nop.m 0
|
|
nop.m 0
|
|
add GR_Parameter_RESULT = 48,sp
|
|
};;
|
|
{ .mmi
|
|
ldfe f8 = [GR_Parameter_RESULT] // Get return result off stack
|
|
.restore sp
|
|
add sp = 64,sp // Restore stack pointer
|
|
mov b0 = GR_SAVE_B0 // Restore return address
|
|
};;
|
|
{ .mib
|
|
mov gp = GR_SAVE_GP // Restore gp
|
|
mov ar.pfs = GR_SAVE_PFS // Restore ar.pfs
|
|
br.ret.sptk b0 // Return
|
|
};;
|
|
|
|
.endp __libm_error_region
|
|
ASM_SIZE_DIRECTIVE(__libm_error_region)
|
|
.type __libm_error_support#,@function
|
|
.global __libm_error_support#
|