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e59ced2384
No bug. Optimization are 1. change control flow for L(more_2x_vec) to fall through to loop and jump for L(less_4x_vec) and L(less_8x_vec). This uses less code size and saves jumps for length > 4x VEC_SIZE. 2. For EVEX/AVX512 move L(less_vec) closer to entry. 3. Avoid complex address mode for length > 2x VEC_SIZE 4. Slightly better aligning code for the loop from the perspective of code size and uops. 5. Align targets so they make full use of their fetch block and if possible cache line. 6. Try and reduce total number of icache lines that will need to be pulled in for a given length. 7. Include "local" version of stosb target. For AVX2/EVEX/AVX512 jumping to the stosb target in the sse2 code section will almost certainly be to a new page. The new version does increase code size marginally by duplicating the target but should get better iTLB behavior as a result. test-memset, test-wmemset, and test-bzero are all passing. Signed-off-by: Noah Goldstein <goldstein.w.n@gmail.com> Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
420 lines
11 KiB
ArmAsm
420 lines
11 KiB
ArmAsm
/* memset/bzero with unaligned store and rep stosb
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Copyright (C) 2016-2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/* memset is implemented as:
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1. Use overlapping store to avoid branch.
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2. If size is less than VEC, use integer register stores.
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3. If size is from VEC_SIZE to 2 * VEC_SIZE, use 2 VEC stores.
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4. If size is from 2 * VEC_SIZE to 4 * VEC_SIZE, use 4 VEC stores.
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5. If size is more to 4 * VEC_SIZE, align to 4 * VEC_SIZE with
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4 VEC stores and store 4 * VEC at a time until done. */
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#include <sysdep.h>
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#ifndef MEMSET_CHK_SYMBOL
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# define MEMSET_CHK_SYMBOL(p,s) MEMSET_SYMBOL(p, s)
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#endif
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#ifndef WMEMSET_CHK_SYMBOL
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# define WMEMSET_CHK_SYMBOL(p,s) WMEMSET_SYMBOL(p, s)
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#endif
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#ifndef XMM0
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# define XMM0 xmm0
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#endif
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#ifndef YMM0
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# define YMM0 ymm0
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#endif
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#ifndef VZEROUPPER
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# if VEC_SIZE > 16
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# define VZEROUPPER vzeroupper
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# define VZEROUPPER_SHORT_RETURN vzeroupper; ret
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# else
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# define VZEROUPPER
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# endif
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#endif
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#ifndef VZEROUPPER_SHORT_RETURN
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# define VZEROUPPER_SHORT_RETURN rep; ret
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#endif
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#ifndef MOVQ
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# if VEC_SIZE > 16
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# define MOVQ vmovq
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# else
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# define MOVQ movq
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# endif
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#endif
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#if VEC_SIZE == 64
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# define LOOP_4X_OFFSET (VEC_SIZE * 4)
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#else
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# define LOOP_4X_OFFSET (0)
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#endif
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#if defined USE_WITH_EVEX || defined USE_WITH_AVX512
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# define END_REG rcx
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# define LOOP_REG rdi
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#else
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# define END_REG rdi
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# define LOOP_REG rdx
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#endif
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#define PAGE_SIZE 4096
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/* Macro to calculate size of small memset block for aligning
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purposes. */
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#define SMALL_MEMSET_ALIGN(mov_sz, ret_sz) (2 * (mov_sz) + (ret_sz) + 1)
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#ifndef SECTION
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# error SECTION is not defined!
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#endif
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.section SECTION(.text),"ax",@progbits
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#if VEC_SIZE == 16 && IS_IN (libc)
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ENTRY (__bzero)
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mov %RDI_LP, %RAX_LP /* Set return value. */
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mov %RSI_LP, %RDX_LP /* Set n. */
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xorl %esi, %esi
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pxor %XMM0, %XMM0
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jmp L(entry_from_bzero)
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END (__bzero)
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weak_alias (__bzero, bzero)
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#endif
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#if IS_IN (libc)
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# if defined SHARED
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ENTRY_CHK (WMEMSET_CHK_SYMBOL (__wmemset_chk, unaligned))
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cmp %RDX_LP, %RCX_LP
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jb HIDDEN_JUMPTARGET (__chk_fail)
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END_CHK (WMEMSET_CHK_SYMBOL (__wmemset_chk, unaligned))
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# endif
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ENTRY (WMEMSET_SYMBOL (__wmemset, unaligned))
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shl $2, %RDX_LP
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WMEMSET_VDUP_TO_VEC0_AND_SET_RETURN (%esi, %rdi)
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jmp L(entry_from_bzero)
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END (WMEMSET_SYMBOL (__wmemset, unaligned))
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#endif
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#if defined SHARED && IS_IN (libc)
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ENTRY_CHK (MEMSET_CHK_SYMBOL (__memset_chk, unaligned))
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cmp %RDX_LP, %RCX_LP
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jb HIDDEN_JUMPTARGET (__chk_fail)
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END_CHK (MEMSET_CHK_SYMBOL (__memset_chk, unaligned))
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#endif
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ENTRY (MEMSET_SYMBOL (__memset, unaligned))
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MEMSET_VDUP_TO_VEC0_AND_SET_RETURN (%esi, %rdi)
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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mov %edx, %edx
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# endif
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L(entry_from_bzero):
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cmpq $VEC_SIZE, %rdx
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jb L(less_vec)
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cmpq $(VEC_SIZE * 2), %rdx
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ja L(more_2x_vec)
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/* From VEC and to 2 * VEC. No branch when size == VEC_SIZE. */
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VMOVU %VEC(0), -VEC_SIZE(%rdi,%rdx)
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VMOVU %VEC(0), (%rdi)
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VZEROUPPER_RETURN
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#if defined USE_MULTIARCH && IS_IN (libc)
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END (MEMSET_SYMBOL (__memset, unaligned))
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# if VEC_SIZE == 16
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ENTRY (__memset_chk_erms)
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cmp %RDX_LP, %RCX_LP
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jb HIDDEN_JUMPTARGET (__chk_fail)
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END (__memset_chk_erms)
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/* Only used to measure performance of REP STOSB. */
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ENTRY (__memset_erms)
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/* Skip zero length. */
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test %RDX_LP, %RDX_LP
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jnz L(stosb)
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movq %rdi, %rax
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ret
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# else
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/* Provide a hidden symbol to debugger. */
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.hidden MEMSET_SYMBOL (__memset, erms)
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ENTRY (MEMSET_SYMBOL (__memset, erms))
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# endif
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L(stosb):
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mov %RDX_LP, %RCX_LP
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movzbl %sil, %eax
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mov %RDI_LP, %RDX_LP
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rep stosb
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mov %RDX_LP, %RAX_LP
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VZEROUPPER_RETURN
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# if VEC_SIZE == 16
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END (__memset_erms)
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# else
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END (MEMSET_SYMBOL (__memset, erms))
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# endif
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# if defined SHARED && IS_IN (libc)
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ENTRY_CHK (MEMSET_CHK_SYMBOL (__memset_chk, unaligned_erms))
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cmp %RDX_LP, %RCX_LP
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jb HIDDEN_JUMPTARGET (__chk_fail)
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END_CHK (MEMSET_CHK_SYMBOL (__memset_chk, unaligned_erms))
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# endif
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ENTRY_P2ALIGN (MEMSET_SYMBOL (__memset, unaligned_erms), 6)
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MEMSET_VDUP_TO_VEC0_AND_SET_RETURN (%esi, %rdi)
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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mov %edx, %edx
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# endif
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cmp $VEC_SIZE, %RDX_LP
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jb L(less_vec)
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cmp $(VEC_SIZE * 2), %RDX_LP
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ja L(stosb_more_2x_vec)
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/* From VEC and to 2 * VEC. No branch when size == VEC_SIZE.
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*/
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VMOVU %VEC(0), (%rax)
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VMOVU %VEC(0), -VEC_SIZE(%rax, %rdx)
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VZEROUPPER_RETURN
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#endif
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.p2align 4,, 10
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L(last_2x_vec):
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#ifdef USE_LESS_VEC_MASK_STORE
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VMOVU %VEC(0), (VEC_SIZE * 2 + LOOP_4X_OFFSET)(%rcx)
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VMOVU %VEC(0), (VEC_SIZE * 3 + LOOP_4X_OFFSET)(%rcx)
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#else
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VMOVU %VEC(0), (VEC_SIZE * -2)(%rdi)
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VMOVU %VEC(0), (VEC_SIZE * -1)(%rdi)
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#endif
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VZEROUPPER_RETURN
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/* If have AVX512 mask instructions put L(less_vec) close to
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entry as it doesn't take much space and is likely a hot target.
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*/
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#ifdef USE_LESS_VEC_MASK_STORE
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.p2align 4,, 10
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L(less_vec):
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/* Less than 1 VEC. */
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# if VEC_SIZE != 16 && VEC_SIZE != 32 && VEC_SIZE != 64
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# error Unsupported VEC_SIZE!
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# endif
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/* Clear high bits from edi. Only keeping bits relevant to page
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cross check. Note that we are using rax which is set in
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MEMSET_VDUP_TO_VEC0_AND_SET_RETURN as ptr from here on out. */
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andl $(PAGE_SIZE - 1), %edi
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/* Check if VEC_SIZE store cross page. Mask stores suffer
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serious performance degradation when it has to fault supress.
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*/
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cmpl $(PAGE_SIZE - VEC_SIZE), %edi
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/* This is generally considered a cold target. */
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ja L(cross_page)
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# if VEC_SIZE > 32
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movq $-1, %rcx
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bzhiq %rdx, %rcx, %rcx
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kmovq %rcx, %k1
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# else
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movl $-1, %ecx
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bzhil %edx, %ecx, %ecx
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kmovd %ecx, %k1
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# endif
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vmovdqu8 %VEC(0), (%rax){%k1}
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VZEROUPPER_RETURN
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# if defined USE_MULTIARCH && IS_IN (libc)
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/* Include L(stosb_local) here if including L(less_vec) between
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L(stosb_more_2x_vec) and ENTRY. This is to cache align the
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L(stosb_more_2x_vec) target. */
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.p2align 4,, 10
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L(stosb_local):
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movzbl %sil, %eax
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mov %RDX_LP, %RCX_LP
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mov %RDI_LP, %RDX_LP
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rep stosb
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mov %RDX_LP, %RAX_LP
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VZEROUPPER_RETURN
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# endif
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#endif
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#if defined USE_MULTIARCH && IS_IN (libc)
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.p2align 4
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L(stosb_more_2x_vec):
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cmp __x86_rep_stosb_threshold(%rip), %RDX_LP
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ja L(stosb_local)
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#endif
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/* Fallthrough goes to L(loop_4x_vec). Tests for memset (2x, 4x]
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and (4x, 8x] jump to target. */
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L(more_2x_vec):
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/* Two different methods of setting up pointers / compare. The
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two methods are based on the fact that EVEX/AVX512 mov
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instructions take more bytes then AVX2/SSE2 mov instructions. As
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well that EVEX/AVX512 machines also have fast LEA_BID. Both
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setup and END_REG to avoid complex address mode. For EVEX/AVX512
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this saves code size and keeps a few targets in one fetch block.
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For AVX2/SSE2 this helps prevent AGU bottlenecks. */
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#if defined USE_WITH_EVEX || defined USE_WITH_AVX512
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/* If EVEX/AVX512 compute END_REG - (VEC_SIZE * 4 +
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LOOP_4X_OFFSET) with LEA_BID. */
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/* END_REG is rcx for EVEX/AVX512. */
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leaq -(VEC_SIZE * 4 + LOOP_4X_OFFSET)(%rdi, %rdx), %END_REG
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#endif
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/* Stores to first 2x VEC before cmp as any path forward will
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require it. */
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VMOVU %VEC(0), (%rax)
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VMOVU %VEC(0), VEC_SIZE(%rax)
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#if !(defined USE_WITH_EVEX || defined USE_WITH_AVX512)
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/* If AVX2/SSE2 compute END_REG (rdi) with ALU. */
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addq %rdx, %END_REG
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#endif
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cmpq $(VEC_SIZE * 4), %rdx
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jbe L(last_2x_vec)
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/* Store next 2x vec regardless. */
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VMOVU %VEC(0), (VEC_SIZE * 2)(%rax)
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VMOVU %VEC(0), (VEC_SIZE * 3)(%rax)
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#if defined USE_WITH_EVEX || defined USE_WITH_AVX512
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/* If LOOP_4X_OFFSET don't readjust LOOP_REG (rdi), just add
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extra offset to addresses in loop. Used for AVX512 to save space
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as no way to get (VEC_SIZE * 4) in imm8. */
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# if LOOP_4X_OFFSET == 0
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subq $-(VEC_SIZE * 4), %LOOP_REG
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# endif
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/* Avoid imm32 compare here to save code size. */
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cmpq %rdi, %rcx
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#else
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addq $-(VEC_SIZE * 4), %END_REG
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cmpq $(VEC_SIZE * 8), %rdx
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#endif
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jbe L(last_4x_vec)
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#if !(defined USE_WITH_EVEX || defined USE_WITH_AVX512)
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/* Set LOOP_REG (rdx). */
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leaq (VEC_SIZE * 4)(%rax), %LOOP_REG
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#endif
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/* Align dst for loop. */
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andq $(VEC_SIZE * -2), %LOOP_REG
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.p2align 4
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L(loop):
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VMOVA %VEC(0), LOOP_4X_OFFSET(%LOOP_REG)
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VMOVA %VEC(0), (VEC_SIZE + LOOP_4X_OFFSET)(%LOOP_REG)
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VMOVA %VEC(0), (VEC_SIZE * 2 + LOOP_4X_OFFSET)(%LOOP_REG)
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VMOVA %VEC(0), (VEC_SIZE * 3 + LOOP_4X_OFFSET)(%LOOP_REG)
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subq $-(VEC_SIZE * 4), %LOOP_REG
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cmpq %END_REG, %LOOP_REG
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jb L(loop)
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.p2align 4,, MOV_SIZE
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L(last_4x_vec):
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VMOVU %VEC(0), LOOP_4X_OFFSET(%END_REG)
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VMOVU %VEC(0), (VEC_SIZE + LOOP_4X_OFFSET)(%END_REG)
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VMOVU %VEC(0), (VEC_SIZE * 2 + LOOP_4X_OFFSET)(%END_REG)
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VMOVU %VEC(0), (VEC_SIZE * 3 + LOOP_4X_OFFSET)(%END_REG)
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L(return):
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#if VEC_SIZE > 16
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ZERO_UPPER_VEC_REGISTERS_RETURN
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#else
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ret
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#endif
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.p2align 4,, 10
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#ifndef USE_LESS_VEC_MASK_STORE
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# if defined USE_MULTIARCH && IS_IN (libc)
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/* If no USE_LESS_VEC_MASK put L(stosb_local) here. Will be in
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range for 2-byte jump encoding. */
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L(stosb_local):
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movzbl %sil, %eax
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mov %RDX_LP, %RCX_LP
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mov %RDI_LP, %RDX_LP
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rep stosb
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mov %RDX_LP, %RAX_LP
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VZEROUPPER_RETURN
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# endif
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/* Define L(less_vec) only if not otherwise defined. */
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.p2align 4
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L(less_vec):
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#endif
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L(cross_page):
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#if VEC_SIZE > 32
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cmpl $32, %edx
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jae L(between_32_63)
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#endif
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#if VEC_SIZE > 16
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cmpl $16, %edx
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jae L(between_16_31)
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#endif
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MOVQ %XMM0, %rdi
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cmpl $8, %edx
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jae L(between_8_15)
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cmpl $4, %edx
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jae L(between_4_7)
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cmpl $1, %edx
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ja L(between_2_3)
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jb L(return)
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movb %sil, (%rax)
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VZEROUPPER_RETURN
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/* Align small targets only if not doing so would cross a fetch
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line. */
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#if VEC_SIZE > 32
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.p2align 4,, SMALL_MEMSET_ALIGN(MOV_SIZE, RET_SIZE)
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/* From 32 to 63. No branch when size == 32. */
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L(between_32_63):
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VMOVU %YMM0, (%rax)
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VMOVU %YMM0, -32(%rax, %rdx)
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VZEROUPPER_RETURN
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#endif
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#if VEC_SIZE >= 32
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.p2align 4,, SMALL_MEMSET_ALIGN(MOV_SIZE, RET_SIZE)
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L(between_16_31):
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/* From 16 to 31. No branch when size == 16. */
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VMOVU %XMM0, (%rax)
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VMOVU %XMM0, -16(%rax, %rdx)
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VZEROUPPER_RETURN
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#endif
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.p2align 4,, SMALL_MEMSET_ALIGN(3, RET_SIZE)
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L(between_8_15):
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/* From 8 to 15. No branch when size == 8. */
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movq %rdi, (%rax)
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movq %rdi, -8(%rax, %rdx)
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VZEROUPPER_RETURN
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.p2align 4,, SMALL_MEMSET_ALIGN(2, RET_SIZE)
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L(between_4_7):
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/* From 4 to 7. No branch when size == 4. */
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movl %edi, (%rax)
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movl %edi, -4(%rax, %rdx)
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VZEROUPPER_RETURN
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.p2align 4,, SMALL_MEMSET_ALIGN(3, RET_SIZE)
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L(between_2_3):
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/* From 2 to 3. No branch when size == 2. */
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movw %di, (%rax)
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movb %dil, -1(%rax, %rdx)
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VZEROUPPER_RETURN
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END (MEMSET_SYMBOL (__memset, unaligned_erms))
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