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fa527f345c
This patch optimizes the performance of memcpy/memmove for A64FX [1] which implements ARMv8-A SVE and has L1 64KB cache per core and L2 8MB cache per NUMA node. The performance optimization makes use of Scalable Vector Register with several techniques such as loop unrolling, memory access alignment, cache zero fill, and software pipelining. SVE assembler code for memcpy/memmove is implemented as Vector Length Agnostic code so theoretically it can be run on any SOC which supports ARMv8-A SVE standard. We confirmed that all testcases have been passed by running 'make check' and 'make xcheck' not only on A64FX but also on ThunderX2. And also we confirmed that the SVE 512 bit vector register performance is roughly 4 times better than Advanced SIMD 128 bit register and 8 times better than scalar 64 bit register by running 'make bench'. [1] https://github.com/fujitsu/A64FX Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com> Reviewed-by: Szabolcs Nagy <Szabolcs.Nagy@arm.com>
39 lines
1.7 KiB
C
39 lines
1.7 KiB
C
/* Define INIT_ARCH so that midr is initialized before use by IFUNCs.
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This file is part of the GNU C Library.
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Copyright (C) 2017-2021 Free Software Foundation, Inc.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <ldsodefs.h>
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#include <sys/auxv.h>
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/* Make glibc MTE-safe on a system that supports MTE in case user code
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enables tag checks independently of the mte_status of glibc. There
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is currently no ABI contract for enabling tag checks in user code,
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but this can be useful for debugging with MTE. */
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#define MTE_ENABLED() (GLRO(dl_hwcap2) & HWCAP2_MTE)
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#define INIT_ARCH() \
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uint64_t __attribute__((unused)) midr = \
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GLRO(dl_aarch64_cpu_features).midr_el1; \
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unsigned __attribute__((unused)) zva_size = \
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GLRO(dl_aarch64_cpu_features).zva_size; \
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bool __attribute__((unused)) bti = \
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HAVE_AARCH64_BTI && GLRO(dl_aarch64_cpu_features).bti; \
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bool __attribute__((unused)) mte = \
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MTE_ENABLED (); \
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bool __attribute__((unused)) sve = \
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GLRO(dl_aarch64_cpu_features).sve;
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