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d5b411854f
A number of functions in the sysdeps/powerpc/powerpc64/ tree don't use or change r2, yet declare a global entry that sets up r2. This patch fixes that problem, and consolidates the ENTRY and EALIGN macros. * sysdeps/powerpc/powerpc64/sysdep.h: Formatting. (NOPS, ENTRY_3): New macros. (ENTRY): Rewrite. (ENTRY_TOCLESS): Define. (EALIGN, EALIGN_W_0, EALIGN_W_1, EALIGN_W_2, EALIGN_W_4, EALIGN_W_5, EALIGN_W_6, EALIGN_W_7, EALIGN_W_8): Delete. * sysdeps/powerpc/powerpc64/a2/memcpy.S: Replace EALIGN with ENTRY. * sysdeps/powerpc/powerpc64/dl-trampoline.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_ceil.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_ceilf.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_floor.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_floorf.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_nearbyint.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_nearbyintf.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_rint.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_rintf.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_round.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_roundf.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_trunc.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_truncf.S: Likewise. * sysdeps/powerpc/powerpc64/memset.S: Likewise. * sysdeps/powerpc/powerpc64/power7/fpu/s_finite.S: Likewise. * sysdeps/powerpc/powerpc64/power7/fpu/s_isinf.S: Likewise. * sysdeps/powerpc/powerpc64/power7/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strstr.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/e_expf.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_cosf.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_sinf.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strcasestr.S: Likewise. * sysdeps/powerpc/powerpc64/addmul_1.S: Use ENTRY_TOCLESS. * sysdeps/powerpc/powerpc64/cell/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_copysign.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_copysignl.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_fabsl.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_llrint.S: Likewise. * sysdeps/powerpc/powerpc64/fpu/s_llrintf.S: Likewise. * sysdeps/powerpc/powerpc64/lshift.S: Likewise. * sysdeps/powerpc/powerpc64/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/mul_1.S: Likewise. * sysdeps/powerpc/powerpc64/power4/memcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power4/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power4/memset.S: Likewise. * sysdeps/powerpc/powerpc64/power4/strncmp.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_ceil.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_ceilf.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_floor.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_floorf.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_llround.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_round.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_roundf.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_trunc.S: Likewise. * sysdeps/powerpc/powerpc64/power5+/fpu/s_truncf.S: Likewise. * sysdeps/powerpc/powerpc64/power5/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/power6/fpu/s_copysign.S: Likewise. * sysdeps/powerpc/powerpc64/power6/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/power6/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power6/memset.S: Likewise. * sysdeps/powerpc/powerpc64/power6x/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/power6x/fpu/s_llrint.S: Likewise. * sysdeps/powerpc/powerpc64/power6x/fpu/s_llround.S: Likewise. * sysdeps/powerpc/powerpc64/power7/add_n.S: Likewise. * sysdeps/powerpc/powerpc64/power7/memchr.S: Likewise. * sysdeps/powerpc/powerpc64/power7/memcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power7/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power7/memmove.S: Likewise. * sysdeps/powerpc/powerpc64/power7/mempcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power7/memrchr.S: Likewise. * sysdeps/powerpc/powerpc64/power7/memset.S: Likewise. * sysdeps/powerpc/powerpc64/power7/rawmemchr.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strcasecmp.S (strcasecmp_l): Likewise. * sysdeps/powerpc/powerpc64/power7/strchr.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strchrnul.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strlen.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strncmp.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strncpy.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strnlen.S: Likewise. * sysdeps/powerpc/powerpc64/power7/strrchr.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S: Likewise. * sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S: Likewise. * sysdeps/powerpc/powerpc64/power8/memcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power8/memset.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strchr.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strlen.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strncmp.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strncpy.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strnlen.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strrchr.S: Likewise. * sysdeps/powerpc/powerpc64/power8/strspn.S: Likewise. * sysdeps/powerpc/powerpc64/power9/strcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power9/strncmp.S: Likewise. * sysdeps/powerpc/powerpc64/strchr.S: Likewise. * sysdeps/powerpc/powerpc64/strcmp.S: Likewise. * sysdeps/powerpc/powerpc64/strlen.S: Likewise. * sysdeps/powerpc/powerpc64/strncmp.S: Likewise. * sysdeps/powerpc/powerpc64/ppc-mcount.S: Store LR earlier. Don't add nop when SHARED. * sysdeps/powerpc/powerpc64/start.S: Fix comment. * sysdeps/powerpc/powerpc64/multiarch/strrchr-power8.S (ENTRY): Don't define. (ENTRY_TOCLESS): Define. * sysdeps/powerpc/powerpc32/sysdep.h (ENTRY_TOCLESS): Define. * sysdeps/powerpc/fpu/s_fma.S: Use ENTRY_TOCLESS. * sysdeps/powerpc/fpu/s_fmaf.S: Likewise.
380 lines
7.9 KiB
ArmAsm
380 lines
7.9 KiB
ArmAsm
/* Optimized strncmp implementation for PowerPC64/POWER9.
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Copyright (C) 2016-2017 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#ifdef __LITTLE_ENDIAN__
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#include <sysdep.h>
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/* Implements the function
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int [r3] strncmp (const char *s1 [r3], const char *s2 [r4], size_t [r5] n)
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The implementation uses unaligned doubleword access to avoid specialized
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code paths depending of data alignment for first 32 bytes and uses
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vectorised loops after that. */
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#ifndef STRNCMP
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# define STRNCMP strncmp
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#endif
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/* TODO: Change this to actual instructions when minimum binutils is upgraded
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to 2.27. Macros are defined below for these newer instructions in order
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to maintain compatibility. */
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# define VCTZLSBB(r,v) .long (0x10010602 | ((r)<<(32-11)) | ((v)<<(32-21)))
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# define VEXTUBRX(t,a,b) .long (0x1000070d \
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| ((t)<<(32-11)) \
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| ((a)<<(32-16)) \
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| ((b)<<(32-21)) )
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# define VCMPNEZB(t,a,b) .long (0x10000507 \
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| ((t)<<(32-11)) \
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| ((a)<<(32-16)) \
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| ((b)<<(32-21)) )
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/* Get 16 bytes for unaligned case.
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reg1: Vector to hold next 16 bytes.
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reg2: Address to read from.
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reg3: Permute control vector. */
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# define GET16BYTES(reg1, reg2, reg3) \
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lvx reg1, 0, reg2; \
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vperm v8, v2, reg1, reg3; \
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vcmpequb. v8, v0, v8; \
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beq cr6, 1f; \
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vspltisb v9, 0; \
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b 2f; \
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.align 4; \
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1: \
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cmplw cr6, r5, r11; \
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ble cr6, 2f; \
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addi r6, reg2, 16; \
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lvx v9, 0, r6; \
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2: \
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vperm reg1, v9, reg1, reg3;
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/* TODO: change this to .machine power9 when minimum binutils
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is upgraded to 2.27. */
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.machine power7
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ENTRY_TOCLESS (STRNCMP, 4)
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/* Check if size is 0. */
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cmpdi cr0, r5, 0
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beq cr0, L(ret0)
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li r0, 0
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/* Check if [s1]+32 or [s2]+32 will cross a 4K page boundary using
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the code:
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(((size_t) s1) % PAGE_SIZE > (PAGE_SIZE - ITER_SIZE))
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with PAGE_SIZE being 4096 and ITER_SIZE begin 32. */
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rldicl r8, r3, 0, 52
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cmpldi cr7, r8, 4096-32
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bgt cr7, L(pagecross)
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rldicl r9, r4, 0, 52
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cmpldi cr7, r9, 4096-32
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bgt cr7, L(pagecross)
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/* For short strings up to 32 bytes, load both s1 and s2 using
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unaligned dwords and compare. */
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ld r7, 0(r3)
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ld r9, 0(r4)
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li r8, 0
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cmpb r8, r7, r8
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cmpb r6, r7, r9
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orc. r8, r8, r6
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bne cr0, L(different1)
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/* If the strings compared are equal, but size is less or equal
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to 8, return 0. */
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cmpldi cr7, r5, 8
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li r9, 0
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ble cr7, L(ret1)
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addi r5, r5, -8
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ld r7, 8(r3)
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ld r9, 8(r4)
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cmpb r8, r7, r8
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cmpb r6, r7, r9
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orc. r8, r8, r6
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bne cr0, L(different1)
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cmpldi cr7, r5, 8
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mr r9, r8
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ble cr7, L(ret1)
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/* Update pointers and size. */
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addi r5, r5, -8
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addi r3, r3, 16
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addi r4, r4, 16
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ld r7, 0(r3)
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ld r9, 0(r4)
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li r8, 0
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cmpb r8, r7, r8
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cmpb r6, r7, r9
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orc. r8, r8, r6
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bne cr0, L(different1)
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cmpldi cr7, r5, 8
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li r9, 0
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ble cr7, L(ret1)
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addi r5, r5, -8
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ld r7, 8(r3)
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ld r9, 8(r4)
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cmpb r8, r7, r8
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cmpb r6, r7, r9
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orc. r8, r8, r6
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bne cr0, L(different1)
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cmpldi cr7, r5, 8
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mr r9, r8
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ble cr7, L(ret1)
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/* Update pointers and size. */
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addi r5, r5, -8
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addi r3, r3, 16
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addi r4, r4, 16
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L(align):
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/* Now it has checked for first 32 bytes, align source1 to doubleword
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and adjust source2 address. */
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vspltisb v0, 0
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vspltisb v2, -1
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or r6, r4, r3
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andi. r6, r6, 0xF
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beq cr0, L(aligned)
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lvsr v6, 0, r4 /* Compute mask. */
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clrldi r6, r4, 60
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subfic r11, r6, 16
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andi. r6, r3, 0xF
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beq cr0, L(s1_align)
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/* Both s1 and s2 are unaligned. */
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GET16BYTES(v5, r4, v6)
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lvsr v10, 0, r3 /* Compute mask. */
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clrldi r6, r3, 60
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subfic r11, r6, 16
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GET16BYTES(v4, r3, v10)
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VCMPNEZB(v7, v5, v4)
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beq cr6, L(match)
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b L(different)
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/* Align s1 to qw and adjust s2 address. */
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.align 4
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L(match):
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cmpldi cr7, r5, 16
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ble cr7, L(ret0)
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subf r5, r11, r5
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add r3, r3, r11
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add r4, r4, r11
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andi. r11, r4, 0xF
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beq cr0, L(aligned)
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lvsr v6, 0, r4
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clrldi r6, r4, 60
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subfic r11, r6, 16
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/* There are 2 loops depending on the input alignment.
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Each loop gets 16 bytes from s1 and s2, checks for null
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and compares them. Loops until a mismatch or null occurs. */
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L(s1_align):
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lvx v4, 0, r3
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GET16BYTES(v5, r4, v6)
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VCMPNEZB(v7, v5, v4)
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bne cr6, L(different)
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cmpldi cr7, r5, 16
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ble cr7, L(ret0)
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addi r5, r5, -16
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addi r3, r3, 16
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addi r4, r4, 16
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lvx v4, 0, r3
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GET16BYTES(v5, r4, v6)
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VCMPNEZB(v7, v5, v4)
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bne cr6, L(different)
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cmpldi cr7, r5, 16
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ble cr7, L(ret0)
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addi r5, r5, -16
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addi r3, r3, 16
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addi r4, r4, 16
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lvx v4, 0, r3
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GET16BYTES(v5, r4, v6)
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VCMPNEZB(v7, v5, v4)
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bne cr6, L(different)
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cmpldi cr7, r5, 16
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ble cr7, L(ret0)
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addi r5, r5, -16
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addi r3, r3, 16
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addi r4, r4, 16
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lvx v4, 0, r3
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GET16BYTES(v5, r4, v6)
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VCMPNEZB(v7, v5, v4)
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bne cr6, L(different)
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cmpldi cr7, r5, 16
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ble cr7, L(ret0)
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addi r5, r5, -16
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addi r3, r3, 16
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addi r4, r4, 16
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b L(s1_align)
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.align 4
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L(aligned):
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lvx v4, 0, r3
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lvx v5, 0, r4
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VCMPNEZB(v7, v5, v4)
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bne cr6, L(different)
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cmpldi cr7, r5, 16
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ble cr7, L(ret0)
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addi r5, r5, -16
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addi r3, r3, 16
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addi r4, r4, 16
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lvx v4, 0, r3
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lvx v5, 0, r4
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VCMPNEZB(v7, v5, v4)
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bne cr6, L(different)
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cmpldi cr7, r5, 16
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ble cr7, L(ret0)
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addi r5, r5, -16
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addi r3, r3, 16
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addi r4, r4, 16
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lvx v4, 0, r3
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lvx v5, 0, r4
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VCMPNEZB(v7, v5, v4)
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bne cr6, L(different)
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cmpldi cr7, r5, 16
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ble cr7, L(ret0)
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addi r5, r5, -16
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addi r3, r3, 16
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addi r4, r4, 16
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lvx v4, 0, r3
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lvx v5, 0, r4
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VCMPNEZB(v7, v5, v4)
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bne cr6, L(different)
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cmpldi cr7, r5, 16
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ble cr7, L(ret0)
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addi r5, r5, -16
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addi r3, r3, 16
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addi r4, r4, 16
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b L(aligned)
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/* Calculate and return the difference. */
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L(different):
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VCTZLSBB(r6, v7)
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cmplw cr7, r5, r6
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ble cr7, L(ret0)
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VEXTUBRX(r5, r6, v4)
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VEXTUBRX(r4, r6, v5)
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subf r3, r4, r5
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extsw r3, r3
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blr
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.align 4
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L(ret0):
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li r9, 0
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L(ret1):
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mr r3, r9
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blr
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/* The code now checks if r8 and r5 are different by issuing a
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cmpb and shifts the result based on its output:
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leadzero = (__builtin_ffsl (z1) - 1);
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leadzero = leadzero > (n-1)*8 ? (n-1)*8 : leadzero;
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r1 = (r1 >> leadzero) & 0xFFUL;
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r2 = (r2 >> leadzero) & 0xFFUL;
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return r1 - r2; */
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.align 4
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L(different1):
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neg r11, r8
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sldi r5, r5, 3
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and r8, r11, r8
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addi r5, r5, -8
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cntlzd r8, r8
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subfic r8, r8, 63
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extsw r8, r8
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cmpld cr7, r8, r5
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ble cr7, L(different2)
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mr r8, r5
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L(different2):
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extsw r8, r8
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srd r7, r7, r8
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srd r9, r9, r8
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rldicl r3, r7, 0, 56
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rldicl r9, r9, 0, 56
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subf r9, r9, 3
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extsw r9, r9
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mr r3, r9
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blr
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/* If unaligned 16 bytes reads across a 4K page boundary, it uses
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a simple byte a byte comparison until the page alignment for s1
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is reached. */
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.align 4
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L(pagecross):
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lbz r7, 0(r3)
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lbz r9, 0(r4)
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subfic r8, r8,4095
|
|
cmplw cr7, r9, r7
|
|
bne cr7, L(byte_ne_3)
|
|
cmpdi cr7, r9, 0
|
|
beq cr7, L(byte_ne_0)
|
|
addi r5, r5, -1
|
|
subf r7, r8, r5
|
|
subf r9, r7, r5
|
|
addi r9, r9, 1
|
|
mtctr r9
|
|
b L(pagecross_loop1)
|
|
|
|
.align 4
|
|
L(pagecross_loop0):
|
|
beq cr7, L(ret0)
|
|
lbz r9, 0(r3)
|
|
lbz r8, 0(r4)
|
|
addi r5, r5, -1
|
|
cmplw cr7, r9, r8
|
|
cmpdi cr5, r9, 0
|
|
bne cr7, L(byte_ne_2)
|
|
beq cr5, L(byte_ne_0)
|
|
L(pagecross_loop1):
|
|
cmpdi cr7, r5, 0
|
|
addi r3, r3, 1
|
|
addi r4, r4, 1
|
|
bdnz L(pagecross_loop0)
|
|
cmpdi cr7, r7, 0
|
|
li r9, 0
|
|
bne+ cr7, L(align)
|
|
b L(ret1)
|
|
|
|
.align 4
|
|
L(byte_ne_0):
|
|
li r7, 0
|
|
L(byte_ne_1):
|
|
subf r9, r9, r7
|
|
extsw r9, r9
|
|
b L(ret1)
|
|
|
|
.align 4
|
|
L(byte_ne_2):
|
|
extsw r7, r9
|
|
mr r9, r8
|
|
b L(byte_ne_1)
|
|
L(byte_ne_3):
|
|
extsw r7, r7
|
|
b L(byte_ne_1)
|
|
END(STRNCMP)
|
|
libc_hidden_builtin_def(strncmp)
|
|
#else
|
|
#include <sysdeps/powerpc/powerpc64/power8/strncmp.S>
|
|
#endif
|