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8d9c92017d
Due to GCC bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58066 __tls_get_addr may be called with 8-byte stack alignment. Although this bug has been fixed in GCC 4.9.4, 5.3 and 6, we can't assume that stack will be always aligned at 16 bytes. Since SSE optimized memory/string functions with aligned SSE register load and store are used in the dynamic linker, we must set DL_RUNTIME_UNALIGNED_VEC_SIZE to 8 so that _dl_runtime_resolve_sse will align the stack before calling _dl_fixup: Dump of assembler code for function _dl_runtime_resolve_sse: 0x00007ffff7deea90 <+0>: push %rbx 0x00007ffff7deea91 <+1>: mov %rsp,%rbx 0x00007ffff7deea94 <+4>: and $0xfffffffffffffff0,%rsp ^^^^^^^^^^^ Align stack to 16 bytes 0x00007ffff7deea98 <+8>: sub $0x100,%rsp 0x00007ffff7deea9f <+15>: mov %rax,0xc0(%rsp) 0x00007ffff7deeaa7 <+23>: mov %rcx,0xc8(%rsp) 0x00007ffff7deeaaf <+31>: mov %rdx,0xd0(%rsp) 0x00007ffff7deeab7 <+39>: mov %rsi,0xd8(%rsp) 0x00007ffff7deeabf <+47>: mov %rdi,0xe0(%rsp) 0x00007ffff7deeac7 <+55>: mov %r8,0xe8(%rsp) 0x00007ffff7deeacf <+63>: mov %r9,0xf0(%rsp) 0x00007ffff7deead7 <+71>: movaps %xmm0,(%rsp) 0x00007ffff7deeadb <+75>: movaps %xmm1,0x10(%rsp) 0x00007ffff7deeae0 <+80>: movaps %xmm2,0x20(%rsp) 0x00007ffff7deeae5 <+85>: movaps %xmm3,0x30(%rsp) 0x00007ffff7deeaea <+90>: movaps %xmm4,0x40(%rsp) 0x00007ffff7deeaef <+95>: movaps %xmm5,0x50(%rsp) 0x00007ffff7deeaf4 <+100>: movaps %xmm6,0x60(%rsp) 0x00007ffff7deeaf9 <+105>: movaps %xmm7,0x70(%rsp) [BZ #19679] * sysdeps/x86_64/dl-trampoline.S (DL_RUNIME_UNALIGNED_VEC_SIZE): Renamed to ... (DL_RUNTIME_UNALIGNED_VEC_SIZE): This. Set to 8. (DL_RUNIME_RESOLVE_REALIGN_STACK): Renamed to ... (DL_RUNTIME_RESOLVE_REALIGN_STACK): This. Updated. (DL_RUNIME_RESOLVE_REALIGN_STACK): Renamed to ... (DL_RUNTIME_RESOLVE_REALIGN_STACK): This. * sysdeps/x86_64/dl-trampoline.h (DL_RUNIME_RESOLVE_REALIGN_STACK): Renamed to ... (DL_RUNTIME_RESOLVE_REALIGN_STACK): This.
543 lines
17 KiB
C
543 lines
17 KiB
C
/* PLT trampolines. x86-64 version.
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Copyright (C) 2009-2016 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#undef REGISTER_SAVE_AREA_RAW
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#ifdef __ILP32__
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/* X32 saves RCX, RDX, RSI, RDI, R8 and R9 plus RAX as well as VEC0 to
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VEC7. */
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# define REGISTER_SAVE_AREA_RAW (8 * 7 + VEC_SIZE * 8)
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#else
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/* X86-64 saves RCX, RDX, RSI, RDI, R8 and R9 plus RAX as well as
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BND0, BND1, BND2, BND3 and VEC0 to VEC7. */
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# define REGISTER_SAVE_AREA_RAW (8 * 7 + 16 * 4 + VEC_SIZE * 8)
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#endif
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#undef REGISTER_SAVE_AREA
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#undef LOCAL_STORAGE_AREA
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#undef BASE
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#if DL_RUNTIME_RESOLVE_REALIGN_STACK
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# define REGISTER_SAVE_AREA (REGISTER_SAVE_AREA_RAW + 8)
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/* Local stack area before jumping to function address: RBX. */
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# define LOCAL_STORAGE_AREA 8
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# define BASE rbx
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# if (REGISTER_SAVE_AREA % VEC_SIZE) != 0
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# error REGISTER_SAVE_AREA must be multples of VEC_SIZE
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# endif
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#else
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# define REGISTER_SAVE_AREA REGISTER_SAVE_AREA_RAW
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/* Local stack area before jumping to function address: All saved
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registers. */
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# define LOCAL_STORAGE_AREA REGISTER_SAVE_AREA
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# define BASE rsp
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# if (REGISTER_SAVE_AREA % 16) != 8
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# error REGISTER_SAVE_AREA must be odd multples of 8
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# endif
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#endif
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.text
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.globl _dl_runtime_resolve
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.hidden _dl_runtime_resolve
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.type _dl_runtime_resolve, @function
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.align 16
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cfi_startproc
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_dl_runtime_resolve:
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cfi_adjust_cfa_offset(16) # Incorporate PLT
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#if DL_RUNTIME_RESOLVE_REALIGN_STACK
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# if LOCAL_STORAGE_AREA != 8
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# error LOCAL_STORAGE_AREA must be 8
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# endif
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pushq %rbx # push subtracts stack by 8.
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cfi_adjust_cfa_offset(8)
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cfi_rel_offset(%rbx, 0)
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mov %RSP_LP, %RBX_LP
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cfi_def_cfa_register(%rbx)
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and $-VEC_SIZE, %RSP_LP
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#endif
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sub $REGISTER_SAVE_AREA, %RSP_LP
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cfi_adjust_cfa_offset(REGISTER_SAVE_AREA)
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# Preserve registers otherwise clobbered.
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movq %rax, REGISTER_SAVE_RAX(%rsp)
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movq %rcx, REGISTER_SAVE_RCX(%rsp)
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movq %rdx, REGISTER_SAVE_RDX(%rsp)
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movq %rsi, REGISTER_SAVE_RSI(%rsp)
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movq %rdi, REGISTER_SAVE_RDI(%rsp)
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movq %r8, REGISTER_SAVE_R8(%rsp)
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movq %r9, REGISTER_SAVE_R9(%rsp)
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VMOV %VEC(0), (REGISTER_SAVE_VEC_OFF)(%rsp)
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VMOV %VEC(1), (REGISTER_SAVE_VEC_OFF + VEC_SIZE)(%rsp)
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VMOV %VEC(2), (REGISTER_SAVE_VEC_OFF + VEC_SIZE * 2)(%rsp)
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VMOV %VEC(3), (REGISTER_SAVE_VEC_OFF + VEC_SIZE * 3)(%rsp)
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VMOV %VEC(4), (REGISTER_SAVE_VEC_OFF + VEC_SIZE * 4)(%rsp)
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VMOV %VEC(5), (REGISTER_SAVE_VEC_OFF + VEC_SIZE * 5)(%rsp)
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VMOV %VEC(6), (REGISTER_SAVE_VEC_OFF + VEC_SIZE * 6)(%rsp)
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VMOV %VEC(7), (REGISTER_SAVE_VEC_OFF + VEC_SIZE * 7)(%rsp)
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#ifndef __ILP32__
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# We also have to preserve bound registers. These are nops if
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# Intel MPX isn't available or disabled.
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# ifdef HAVE_MPX_SUPPORT
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bndmov %bnd0, REGISTER_SAVE_BND0(%rsp)
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bndmov %bnd1, REGISTER_SAVE_BND1(%rsp)
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bndmov %bnd2, REGISTER_SAVE_BND2(%rsp)
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bndmov %bnd3, REGISTER_SAVE_BND3(%rsp)
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# else
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# if REGISTER_SAVE_BND0 == 0
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.byte 0x66,0x0f,0x1b,0x04,0x24
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# else
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.byte 0x66,0x0f,0x1b,0x44,0x24,REGISTER_SAVE_BND0
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# endif
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.byte 0x66,0x0f,0x1b,0x4c,0x24,REGISTER_SAVE_BND1
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.byte 0x66,0x0f,0x1b,0x54,0x24,REGISTER_SAVE_BND2
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.byte 0x66,0x0f,0x1b,0x5c,0x24,REGISTER_SAVE_BND3
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# endif
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#endif
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# Copy args pushed by PLT in register.
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# %rdi: link_map, %rsi: reloc_index
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mov (LOCAL_STORAGE_AREA + 8)(%BASE), %RSI_LP
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mov LOCAL_STORAGE_AREA(%BASE), %RDI_LP
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call _dl_fixup # Call resolver.
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mov %RAX_LP, %R11_LP # Save return value
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#ifndef __ILP32__
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# Restore bound registers. These are nops if Intel MPX isn't
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# avaiable or disabled.
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# ifdef HAVE_MPX_SUPPORT
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bndmov REGISTER_SAVE_BND3(%rsp), %bnd3
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bndmov REGISTER_SAVE_BND2(%rsp), %bnd2
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bndmov REGISTER_SAVE_BND1(%rsp), %bnd1
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bndmov REGISTER_SAVE_BND0(%rsp), %bnd0
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# else
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.byte 0x66,0x0f,0x1a,0x5c,0x24,REGISTER_SAVE_BND3
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.byte 0x66,0x0f,0x1a,0x54,0x24,REGISTER_SAVE_BND2
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.byte 0x66,0x0f,0x1a,0x4c,0x24,REGISTER_SAVE_BND1
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# if REGISTER_SAVE_BND0 == 0
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.byte 0x66,0x0f,0x1a,0x04,0x24
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# else
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.byte 0x66,0x0f,0x1a,0x44,0x24,REGISTER_SAVE_BND0
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# endif
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# endif
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#endif
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# Get register content back.
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movq REGISTER_SAVE_R9(%rsp), %r9
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movq REGISTER_SAVE_R8(%rsp), %r8
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movq REGISTER_SAVE_RDI(%rsp), %rdi
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movq REGISTER_SAVE_RSI(%rsp), %rsi
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movq REGISTER_SAVE_RDX(%rsp), %rdx
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movq REGISTER_SAVE_RCX(%rsp), %rcx
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movq REGISTER_SAVE_RAX(%rsp), %rax
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VMOV (REGISTER_SAVE_VEC_OFF)(%rsp), %VEC(0)
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VMOV (REGISTER_SAVE_VEC_OFF + VEC_SIZE)(%rsp), %VEC(1)
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VMOV (REGISTER_SAVE_VEC_OFF + VEC_SIZE * 2)(%rsp), %VEC(2)
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VMOV (REGISTER_SAVE_VEC_OFF + VEC_SIZE * 3)(%rsp), %VEC(3)
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VMOV (REGISTER_SAVE_VEC_OFF + VEC_SIZE * 4)(%rsp), %VEC(4)
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VMOV (REGISTER_SAVE_VEC_OFF + VEC_SIZE * 5)(%rsp), %VEC(5)
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VMOV (REGISTER_SAVE_VEC_OFF + VEC_SIZE * 6)(%rsp), %VEC(6)
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VMOV (REGISTER_SAVE_VEC_OFF + VEC_SIZE * 7)(%rsp), %VEC(7)
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#if DL_RUNTIME_RESOLVE_REALIGN_STACK
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mov %RBX_LP, %RSP_LP
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cfi_def_cfa_register(%rsp)
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movq (%rsp), %rbx
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cfi_restore(%rbx)
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#endif
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# Adjust stack(PLT did 2 pushes)
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add $(LOCAL_STORAGE_AREA + 16), %RSP_LP
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cfi_adjust_cfa_offset(-(LOCAL_STORAGE_AREA + 16))
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# Preserve bound registers.
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PRESERVE_BND_REGS_PREFIX
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jmp *%r11 # Jump to function address.
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cfi_endproc
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.size _dl_runtime_resolve, .-_dl_runtime_resolve
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#ifndef PROF
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# if (LR_VECTOR_OFFSET % VEC_SIZE) != 0
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# error LR_VECTOR_OFFSET must be multples of VEC_SIZE
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# endif
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.globl _dl_runtime_profile
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.hidden _dl_runtime_profile
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.type _dl_runtime_profile, @function
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.align 16
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_dl_runtime_profile:
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cfi_startproc
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cfi_adjust_cfa_offset(16) # Incorporate PLT
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/* The La_x86_64_regs data structure pointed to by the
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fourth paramater must be VEC_SIZE-byte aligned. This must
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be explicitly enforced. We have the set up a dynamically
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sized stack frame. %rbx points to the top half which
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has a fixed size and preserves the original stack pointer. */
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sub $32, %RSP_LP # Allocate the local storage.
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cfi_adjust_cfa_offset(32)
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movq %rbx, (%rsp)
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cfi_rel_offset(%rbx, 0)
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/* On the stack:
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56(%rbx) parameter #1
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48(%rbx) return address
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40(%rbx) reloc index
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32(%rbx) link_map
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24(%rbx) La_x86_64_regs pointer
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16(%rbx) framesize
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8(%rbx) rax
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(%rbx) rbx
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*/
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movq %rax, 8(%rsp)
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mov %RSP_LP, %RBX_LP
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cfi_def_cfa_register(%rbx)
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/* Actively align the La_x86_64_regs structure. */
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and $-VEC_SIZE, %RSP_LP
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/* sizeof(La_x86_64_regs). Need extra space for 8 SSE registers
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to detect if any xmm0-xmm7 registers are changed by audit
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module. */
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sub $(LR_SIZE + XMM_SIZE*8), %RSP_LP
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movq %rsp, 24(%rbx)
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/* Fill the La_x86_64_regs structure. */
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movq %rdx, LR_RDX_OFFSET(%rsp)
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movq %r8, LR_R8_OFFSET(%rsp)
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movq %r9, LR_R9_OFFSET(%rsp)
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movq %rcx, LR_RCX_OFFSET(%rsp)
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movq %rsi, LR_RSI_OFFSET(%rsp)
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movq %rdi, LR_RDI_OFFSET(%rsp)
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movq %rbp, LR_RBP_OFFSET(%rsp)
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lea 48(%rbx), %RAX_LP
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movq %rax, LR_RSP_OFFSET(%rsp)
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/* We always store the XMM registers even if AVX is available.
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This is to provide backward binary compatibility for existing
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audit modules. */
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movaps %xmm0, (LR_XMM_OFFSET)(%rsp)
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movaps %xmm1, (LR_XMM_OFFSET + XMM_SIZE)(%rsp)
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movaps %xmm2, (LR_XMM_OFFSET + XMM_SIZE*2)(%rsp)
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movaps %xmm3, (LR_XMM_OFFSET + XMM_SIZE*3)(%rsp)
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movaps %xmm4, (LR_XMM_OFFSET + XMM_SIZE*4)(%rsp)
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movaps %xmm5, (LR_XMM_OFFSET + XMM_SIZE*5)(%rsp)
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movaps %xmm6, (LR_XMM_OFFSET + XMM_SIZE*6)(%rsp)
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movaps %xmm7, (LR_XMM_OFFSET + XMM_SIZE*7)(%rsp)
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# ifndef __ILP32__
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# ifdef HAVE_MPX_SUPPORT
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bndmov %bnd0, (LR_BND_OFFSET)(%rsp) # Preserve bound
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bndmov %bnd1, (LR_BND_OFFSET + BND_SIZE)(%rsp) # registers. Nops if
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bndmov %bnd2, (LR_BND_OFFSET + BND_SIZE*2)(%rsp) # MPX not available
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bndmov %bnd3, (LR_BND_OFFSET + BND_SIZE*3)(%rsp) # or disabled.
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# else
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.byte 0x66,0x0f,0x1b,0x84,0x24;.long (LR_BND_OFFSET)
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.byte 0x66,0x0f,0x1b,0x8c,0x24;.long (LR_BND_OFFSET + BND_SIZE)
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.byte 0x66,0x0f,0x1b,0x94,0x24;.long (LR_BND_OFFSET + BND_SIZE*2)
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.byte 0x66,0x0f,0x1b,0x9c,0x24;.long (LR_BND_OFFSET + BND_SIZE*3)
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# endif
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# endif
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# ifdef RESTORE_AVX
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/* This is to support AVX audit modules. */
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VMOVA %VEC(0), (LR_VECTOR_OFFSET)(%rsp)
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VMOVA %VEC(1), (LR_VECTOR_OFFSET + VECTOR_SIZE)(%rsp)
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VMOVA %VEC(2), (LR_VECTOR_OFFSET + VECTOR_SIZE*2)(%rsp)
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VMOVA %VEC(3), (LR_VECTOR_OFFSET + VECTOR_SIZE*3)(%rsp)
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VMOVA %VEC(4), (LR_VECTOR_OFFSET + VECTOR_SIZE*4)(%rsp)
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VMOVA %VEC(5), (LR_VECTOR_OFFSET + VECTOR_SIZE*5)(%rsp)
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VMOVA %VEC(6), (LR_VECTOR_OFFSET + VECTOR_SIZE*6)(%rsp)
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VMOVA %VEC(7), (LR_VECTOR_OFFSET + VECTOR_SIZE*7)(%rsp)
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/* Save xmm0-xmm7 registers to detect if any of them are
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changed by audit module. */
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vmovdqa %xmm0, (LR_SIZE)(%rsp)
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vmovdqa %xmm1, (LR_SIZE + XMM_SIZE)(%rsp)
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vmovdqa %xmm2, (LR_SIZE + XMM_SIZE*2)(%rsp)
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vmovdqa %xmm3, (LR_SIZE + XMM_SIZE*3)(%rsp)
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vmovdqa %xmm4, (LR_SIZE + XMM_SIZE*4)(%rsp)
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vmovdqa %xmm5, (LR_SIZE + XMM_SIZE*5)(%rsp)
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vmovdqa %xmm6, (LR_SIZE + XMM_SIZE*6)(%rsp)
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vmovdqa %xmm7, (LR_SIZE + XMM_SIZE*7)(%rsp)
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# endif
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mov %RSP_LP, %RCX_LP # La_x86_64_regs pointer to %rcx.
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mov 48(%rbx), %RDX_LP # Load return address if needed.
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mov 40(%rbx), %RSI_LP # Copy args pushed by PLT in register.
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mov 32(%rbx), %RDI_LP # %rdi: link_map, %rsi: reloc_index
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lea 16(%rbx), %R8_LP # Address of framesize
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call _dl_profile_fixup # Call resolver.
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mov %RAX_LP, %R11_LP # Save return value.
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movq 8(%rbx), %rax # Get back register content.
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movq LR_RDX_OFFSET(%rsp), %rdx
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movq LR_R8_OFFSET(%rsp), %r8
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movq LR_R9_OFFSET(%rsp), %r9
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movaps (LR_XMM_OFFSET)(%rsp), %xmm0
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movaps (LR_XMM_OFFSET + XMM_SIZE)(%rsp), %xmm1
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movaps (LR_XMM_OFFSET + XMM_SIZE*2)(%rsp), %xmm2
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movaps (LR_XMM_OFFSET + XMM_SIZE*3)(%rsp), %xmm3
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movaps (LR_XMM_OFFSET + XMM_SIZE*4)(%rsp), %xmm4
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movaps (LR_XMM_OFFSET + XMM_SIZE*5)(%rsp), %xmm5
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movaps (LR_XMM_OFFSET + XMM_SIZE*6)(%rsp), %xmm6
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movaps (LR_XMM_OFFSET + XMM_SIZE*7)(%rsp), %xmm7
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# ifdef RESTORE_AVX
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/* Check if any xmm0-xmm7 registers are changed by audit
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module. */
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vpcmpeqq (LR_SIZE)(%rsp), %xmm0, %xmm8
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vpmovmskb %xmm8, %esi
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cmpl $0xffff, %esi
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je 2f
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vmovdqa %xmm0, (LR_VECTOR_OFFSET)(%rsp)
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jmp 1f
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2: VMOVA (LR_VECTOR_OFFSET)(%rsp), %VEC(0)
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vmovdqa %xmm0, (LR_XMM_OFFSET)(%rsp)
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1: vpcmpeqq (LR_SIZE + XMM_SIZE)(%rsp), %xmm1, %xmm8
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vpmovmskb %xmm8, %esi
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cmpl $0xffff, %esi
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je 2f
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vmovdqa %xmm1, (LR_VECTOR_OFFSET + VECTOR_SIZE)(%rsp)
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jmp 1f
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2: VMOVA (LR_VECTOR_OFFSET + VECTOR_SIZE)(%rsp), %VEC(1)
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vmovdqa %xmm1, (LR_XMM_OFFSET + XMM_SIZE)(%rsp)
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1: vpcmpeqq (LR_SIZE + XMM_SIZE*2)(%rsp), %xmm2, %xmm8
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vpmovmskb %xmm8, %esi
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cmpl $0xffff, %esi
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je 2f
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vmovdqa %xmm2, (LR_VECTOR_OFFSET + VECTOR_SIZE*2)(%rsp)
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jmp 1f
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2: VMOVA (LR_VECTOR_OFFSET + VECTOR_SIZE*2)(%rsp), %VEC(2)
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vmovdqa %xmm2, (LR_XMM_OFFSET + XMM_SIZE*2)(%rsp)
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1: vpcmpeqq (LR_SIZE + XMM_SIZE*3)(%rsp), %xmm3, %xmm8
|
|
vpmovmskb %xmm8, %esi
|
|
cmpl $0xffff, %esi
|
|
je 2f
|
|
vmovdqa %xmm3, (LR_VECTOR_OFFSET + VECTOR_SIZE*3)(%rsp)
|
|
jmp 1f
|
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2: VMOVA (LR_VECTOR_OFFSET + VECTOR_SIZE*3)(%rsp), %VEC(3)
|
|
vmovdqa %xmm3, (LR_XMM_OFFSET + XMM_SIZE*3)(%rsp)
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|
|
|
1: vpcmpeqq (LR_SIZE + XMM_SIZE*4)(%rsp), %xmm4, %xmm8
|
|
vpmovmskb %xmm8, %esi
|
|
cmpl $0xffff, %esi
|
|
je 2f
|
|
vmovdqa %xmm4, (LR_VECTOR_OFFSET + VECTOR_SIZE*4)(%rsp)
|
|
jmp 1f
|
|
2: VMOVA (LR_VECTOR_OFFSET + VECTOR_SIZE*4)(%rsp), %VEC(4)
|
|
vmovdqa %xmm4, (LR_XMM_OFFSET + XMM_SIZE*4)(%rsp)
|
|
|
|
1: vpcmpeqq (LR_SIZE + XMM_SIZE*5)(%rsp), %xmm5, %xmm8
|
|
vpmovmskb %xmm8, %esi
|
|
cmpl $0xffff, %esi
|
|
je 2f
|
|
vmovdqa %xmm5, (LR_VECTOR_OFFSET + VECTOR_SIZE*5)(%rsp)
|
|
jmp 1f
|
|
2: VMOVA (LR_VECTOR_OFFSET + VECTOR_SIZE*5)(%rsp), %VEC(5)
|
|
vmovdqa %xmm5, (LR_XMM_OFFSET + XMM_SIZE*5)(%rsp)
|
|
|
|
1: vpcmpeqq (LR_SIZE + XMM_SIZE*6)(%rsp), %xmm6, %xmm8
|
|
vpmovmskb %xmm8, %esi
|
|
cmpl $0xffff, %esi
|
|
je 2f
|
|
vmovdqa %xmm6, (LR_VECTOR_OFFSET + VECTOR_SIZE*6)(%rsp)
|
|
jmp 1f
|
|
2: VMOVA (LR_VECTOR_OFFSET + VECTOR_SIZE*6)(%rsp), %VEC(6)
|
|
vmovdqa %xmm6, (LR_XMM_OFFSET + XMM_SIZE*6)(%rsp)
|
|
|
|
1: vpcmpeqq (LR_SIZE + XMM_SIZE*7)(%rsp), %xmm7, %xmm8
|
|
vpmovmskb %xmm8, %esi
|
|
cmpl $0xffff, %esi
|
|
je 2f
|
|
vmovdqa %xmm7, (LR_VECTOR_OFFSET + VECTOR_SIZE*7)(%rsp)
|
|
jmp 1f
|
|
2: VMOVA (LR_VECTOR_OFFSET + VECTOR_SIZE*7)(%rsp), %VEC(7)
|
|
vmovdqa %xmm7, (LR_XMM_OFFSET + XMM_SIZE*7)(%rsp)
|
|
|
|
1:
|
|
# endif
|
|
|
|
# ifndef __ILP32__
|
|
# ifdef HAVE_MPX_SUPPORT
|
|
bndmov (LR_BND_OFFSET)(%rsp), %bnd0 # Restore bound
|
|
bndmov (LR_BND_OFFSET + BND_SIZE)(%rsp), %bnd1 # registers.
|
|
bndmov (LR_BND_OFFSET + BND_SIZE*2)(%rsp), %bnd2
|
|
bndmov (LR_BND_OFFSET + BND_SIZE*3)(%rsp), %bnd3
|
|
# else
|
|
.byte 0x66,0x0f,0x1a,0x84,0x24;.long (LR_BND_OFFSET)
|
|
.byte 0x66,0x0f,0x1a,0x8c,0x24;.long (LR_BND_OFFSET + BND_SIZE)
|
|
.byte 0x66,0x0f,0x1a,0x94,0x24;.long (LR_BND_OFFSET + BND_SIZE*2)
|
|
.byte 0x66,0x0f,0x1a,0x9c,0x24;.long (LR_BND_OFFSET + BND_SIZE*3)
|
|
# endif
|
|
# endif
|
|
|
|
mov 16(%rbx), %R10_LP # Anything in framesize?
|
|
test %R10_LP, %R10_LP
|
|
PRESERVE_BND_REGS_PREFIX
|
|
jns 3f
|
|
|
|
/* There's nothing in the frame size, so there
|
|
will be no call to the _dl_call_pltexit. */
|
|
|
|
/* Get back registers content. */
|
|
movq LR_RCX_OFFSET(%rsp), %rcx
|
|
movq LR_RSI_OFFSET(%rsp), %rsi
|
|
movq LR_RDI_OFFSET(%rsp), %rdi
|
|
|
|
mov %RBX_LP, %RSP_LP
|
|
movq (%rsp), %rbx
|
|
cfi_restore(%rbx)
|
|
cfi_def_cfa_register(%rsp)
|
|
|
|
add $48, %RSP_LP # Adjust the stack to the return value
|
|
# (eats the reloc index and link_map)
|
|
cfi_adjust_cfa_offset(-48)
|
|
PRESERVE_BND_REGS_PREFIX
|
|
jmp *%r11 # Jump to function address.
|
|
|
|
3:
|
|
cfi_adjust_cfa_offset(48)
|
|
cfi_rel_offset(%rbx, 0)
|
|
cfi_def_cfa_register(%rbx)
|
|
|
|
/* At this point we need to prepare new stack for the function
|
|
which has to be called. We copy the original stack to a
|
|
temporary buffer of the size specified by the 'framesize'
|
|
returned from _dl_profile_fixup */
|
|
|
|
lea LR_RSP_OFFSET(%rbx), %RSI_LP # stack
|
|
add $8, %R10_LP
|
|
and $-16, %R10_LP
|
|
mov %R10_LP, %RCX_LP
|
|
sub %R10_LP, %RSP_LP
|
|
mov %RSP_LP, %RDI_LP
|
|
shr $3, %RCX_LP
|
|
rep
|
|
movsq
|
|
|
|
movq 24(%rdi), %rcx # Get back register content.
|
|
movq 32(%rdi), %rsi
|
|
movq 40(%rdi), %rdi
|
|
|
|
PRESERVE_BND_REGS_PREFIX
|
|
call *%r11
|
|
|
|
mov 24(%rbx), %RSP_LP # Drop the copied stack content
|
|
|
|
/* Now we have to prepare the La_x86_64_retval structure for the
|
|
_dl_call_pltexit. The La_x86_64_regs is being pointed by rsp now,
|
|
so we just need to allocate the sizeof(La_x86_64_retval) space on
|
|
the stack, since the alignment has already been taken care of. */
|
|
# ifdef RESTORE_AVX
|
|
/* sizeof(La_x86_64_retval). Need extra space for 2 SSE
|
|
registers to detect if xmm0/xmm1 registers are changed
|
|
by audit module. */
|
|
sub $(LRV_SIZE + XMM_SIZE*2), %RSP_LP
|
|
# else
|
|
sub $LRV_SIZE, %RSP_LP # sizeof(La_x86_64_retval)
|
|
# endif
|
|
mov %RSP_LP, %RCX_LP # La_x86_64_retval argument to %rcx.
|
|
|
|
/* Fill in the La_x86_64_retval structure. */
|
|
movq %rax, LRV_RAX_OFFSET(%rcx)
|
|
movq %rdx, LRV_RDX_OFFSET(%rcx)
|
|
|
|
movaps %xmm0, LRV_XMM0_OFFSET(%rcx)
|
|
movaps %xmm1, LRV_XMM1_OFFSET(%rcx)
|
|
|
|
# ifdef RESTORE_AVX
|
|
/* This is to support AVX audit modules. */
|
|
VMOVA %VEC(0), LRV_VECTOR0_OFFSET(%rcx)
|
|
VMOVA %VEC(1), LRV_VECTOR1_OFFSET(%rcx)
|
|
|
|
/* Save xmm0/xmm1 registers to detect if they are changed
|
|
by audit module. */
|
|
vmovdqa %xmm0, (LRV_SIZE)(%rcx)
|
|
vmovdqa %xmm1, (LRV_SIZE + XMM_SIZE)(%rcx)
|
|
# endif
|
|
|
|
# ifndef __ILP32__
|
|
# ifdef HAVE_MPX_SUPPORT
|
|
bndmov %bnd0, LRV_BND0_OFFSET(%rcx) # Preserve returned bounds.
|
|
bndmov %bnd1, LRV_BND1_OFFSET(%rcx)
|
|
# else
|
|
.byte 0x66,0x0f,0x1b,0x81;.long (LRV_BND0_OFFSET)
|
|
.byte 0x66,0x0f,0x1b,0x89;.long (LRV_BND1_OFFSET)
|
|
# endif
|
|
# endif
|
|
|
|
fstpt LRV_ST0_OFFSET(%rcx)
|
|
fstpt LRV_ST1_OFFSET(%rcx)
|
|
|
|
movq 24(%rbx), %rdx # La_x86_64_regs argument to %rdx.
|
|
movq 40(%rbx), %rsi # Copy args pushed by PLT in register.
|
|
movq 32(%rbx), %rdi # %rdi: link_map, %rsi: reloc_index
|
|
call _dl_call_pltexit
|
|
|
|
/* Restore return registers. */
|
|
movq LRV_RAX_OFFSET(%rsp), %rax
|
|
movq LRV_RDX_OFFSET(%rsp), %rdx
|
|
|
|
movaps LRV_XMM0_OFFSET(%rsp), %xmm0
|
|
movaps LRV_XMM1_OFFSET(%rsp), %xmm1
|
|
|
|
# ifdef RESTORE_AVX
|
|
/* Check if xmm0/xmm1 registers are changed by audit module. */
|
|
vpcmpeqq (LRV_SIZE)(%rsp), %xmm0, %xmm2
|
|
vpmovmskb %xmm2, %esi
|
|
cmpl $0xffff, %esi
|
|
jne 1f
|
|
VMOVA LRV_VECTOR0_OFFSET(%rsp), %VEC(0)
|
|
|
|
1: vpcmpeqq (LRV_SIZE + XMM_SIZE)(%rsp), %xmm1, %xmm2
|
|
vpmovmskb %xmm2, %esi
|
|
cmpl $0xffff, %esi
|
|
jne 1f
|
|
VMOVA LRV_VECTOR1_OFFSET(%rsp), %VEC(1)
|
|
|
|
1:
|
|
# endif
|
|
|
|
# ifndef __ILP32__
|
|
# ifdef HAVE_MPX_SUPPORT
|
|
bndmov LRV_BND0_OFFSET(%rsp), %bnd0 # Restore bound registers.
|
|
bndmov LRV_BND1_OFFSET(%rsp), %bnd1
|
|
# else
|
|
.byte 0x66,0x0f,0x1a,0x84,0x24;.long (LRV_BND0_OFFSET)
|
|
.byte 0x66,0x0f,0x1a,0x8c,0x24;.long (LRV_BND1_OFFSET)
|
|
# endif
|
|
# endif
|
|
|
|
fldt LRV_ST1_OFFSET(%rsp)
|
|
fldt LRV_ST0_OFFSET(%rsp)
|
|
|
|
mov %RBX_LP, %RSP_LP
|
|
movq (%rsp), %rbx
|
|
cfi_restore(%rbx)
|
|
cfi_def_cfa_register(%rsp)
|
|
|
|
add $48, %RSP_LP # Adjust the stack to the return value
|
|
# (eats the reloc index and link_map)
|
|
cfi_adjust_cfa_offset(-48)
|
|
PRESERVE_BND_REGS_PREFIX
|
|
retq
|
|
|
|
cfi_endproc
|
|
.size _dl_runtime_profile, .-_dl_runtime_profile
|
|
#endif
|