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91 lines
2.5 KiB
ArmAsm
91 lines
2.5 KiB
ArmAsm
/* PLT trampolines.
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Copyright (C) 2022-2023 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include <sys/asm.h>
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/* Assembler veneer called from the PLT header code for lazy loading.
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The PLT header passes its own args in t0-t2. */
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#ifdef __loongarch_soft_float
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#define FRAME_SIZE (-((-10 * SZREG) & ALMASK))
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#else
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#define FRAME_SIZE (-((-10 * SZREG - 8 * SZFREG) & ALMASK))
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#endif
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ENTRY (_dl_runtime_resolve)
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/* Save arguments to stack. */
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ADDI sp, sp, -FRAME_SIZE
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REG_S ra, sp, 9*SZREG
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REG_S a0, sp, 1*SZREG
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REG_S a1, sp, 2*SZREG
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REG_S a2, sp, 3*SZREG
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REG_S a3, sp, 4*SZREG
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REG_S a4, sp, 5*SZREG
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REG_S a5, sp, 6*SZREG
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REG_S a6, sp, 7*SZREG
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REG_S a7, sp, 8*SZREG
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#ifndef __loongarch_soft_float
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FREG_S fa0, sp, 10*SZREG + 0*SZFREG
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FREG_S fa1, sp, 10*SZREG + 1*SZFREG
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FREG_S fa2, sp, 10*SZREG + 2*SZFREG
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FREG_S fa3, sp, 10*SZREG + 3*SZFREG
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FREG_S fa4, sp, 10*SZREG + 4*SZFREG
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FREG_S fa5, sp, 10*SZREG + 5*SZFREG
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FREG_S fa6, sp, 10*SZREG + 6*SZFREG
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FREG_S fa7, sp, 10*SZREG + 7*SZFREG
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#endif
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/* Update .got.plt and obtain runtime address of callee */
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SLLI a1, t1, 1
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or a0, t0, zero
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ADD a1, a1, t1
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la a2, _dl_fixup
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jirl ra, a2, 0
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or t1, v0, zero
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/* Restore arguments from stack. */
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REG_L ra, sp, 9*SZREG
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REG_L a0, sp, 1*SZREG
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REG_L a1, sp, 2*SZREG
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REG_L a2, sp, 3*SZREG
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REG_L a3, sp, 4*SZREG
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REG_L a4, sp, 5*SZREG
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REG_L a5, sp, 6*SZREG
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REG_L a6, sp, 7*SZREG
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REG_L a7, sp, 8*SZREG
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#ifndef __loongarch_soft_float
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FREG_L fa0, sp, 10*SZREG + 0*SZFREG
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FREG_L fa1, sp, 10*SZREG + 1*SZFREG
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FREG_L fa2, sp, 10*SZREG + 2*SZFREG
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FREG_L fa3, sp, 10*SZREG + 3*SZFREG
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FREG_L fa4, sp, 10*SZREG + 4*SZFREG
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FREG_L fa5, sp, 10*SZREG + 5*SZFREG
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FREG_L fa6, sp, 10*SZREG + 6*SZFREG
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FREG_L fa7, sp, 10*SZREG + 7*SZFREG
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#endif
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ADDI sp, sp, FRAME_SIZE
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/* Invoke the callee. */
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jirl zero, t1, 0
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END (_dl_runtime_resolve)
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