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f43cb35c9b
If assembler doesn't support AVX512DQ, _dl_runtime_resolve_avx is used to save the first 8 vector registers, which only saves the lower 256 bits of vector register, for lazy binding. When it is called on AVX512 platform, the upper 256 bits of ZMM registers are clobbered. Parameters passed in ZMM registers will be wrong when the function is called the first time. This patch requires binutils 2.24, whose assembler can store and load ZMM registers, to build x86-64 glibc. Since mathvec library needs assembler support for AVX512DQ, we disable mathvec if assembler doesn't support AVX512DQ. [BZ #20139] * config.h.in (HAVE_AVX512_ASM_SUPPORT): Renamed to ... (HAVE_AVX512DQ_ASM_SUPPORT): This. * sysdeps/x86_64/configure.ac: Require assembler from binutils 2.24 or above. (HAVE_AVX512_ASM_SUPPORT): Removed. (HAVE_AVX512DQ_ASM_SUPPORT): New. * sysdeps/x86_64/configure: Regenerated. * sysdeps/x86_64/dl-trampoline.S: Make HAVE_AVX512_ASM_SUPPORT check unconditional. * sysdeps/x86_64/multiarch/ifunc-impl-list.c: Likewise. * sysdeps/x86_64/multiarch/memcpy.S: Likewise. * sysdeps/x86_64/multiarch/memcpy_chk.S: Likewise. * sysdeps/x86_64/multiarch/memmove-avx512-no-vzeroupper.S: Likewise. * sysdeps/x86_64/multiarch/memmove-avx512-unaligned-erms.S: Likewise. * sysdeps/x86_64/multiarch/memmove.S: Likewise. * sysdeps/x86_64/multiarch/memmove_chk.S: Likewise. * sysdeps/x86_64/multiarch/mempcpy.S: Likewise. * sysdeps/x86_64/multiarch/mempcpy_chk.S: Likewise. * sysdeps/x86_64/multiarch/memset-avx512-no-vzeroupper.S: Likewise. * sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S: Likewise. * sysdeps/x86_64/multiarch/memset.S: Likewise. * sysdeps/x86_64/multiarch/memset_chk.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core_avx512.S: Check HAVE_AVX512DQ_ASM_SUPPORT instead of HAVE_AVX512_ASM_SUPPORT. * sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx51: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core_avx512.S: Likewise.
195 lines
4.2 KiB
ArmAsm
195 lines
4.2 KiB
ArmAsm
/* memset optimized with AVX512 for KNL hardware.
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Copyright (C) 2015-2016 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#if IS_IN (libc)
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#include "asm-syntax.h"
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#ifndef MEMSET
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# define MEMSET __memset_avx512_no_vzeroupper
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# define MEMSET_CHK __memset_chk_avx512_no_vzeroupper
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#endif
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.section .text.avx512,"ax",@progbits
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#if defined PIC
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ENTRY (MEMSET_CHK)
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cmpq %rdx, %rcx
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jb HIDDEN_JUMPTARGET (__chk_fail)
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END (MEMSET_CHK)
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#endif
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ENTRY (MEMSET)
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vpxor %xmm0, %xmm0, %xmm0
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vmovd %esi, %xmm1
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lea (%rdi, %rdx), %rsi
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mov %rdi, %rax
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vpshufb %xmm0, %xmm1, %xmm0
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cmp $16, %rdx
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jb L(less_16bytes)
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cmp $512, %rdx
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vbroadcastss %xmm0, %zmm2
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ja L(512bytesormore)
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cmp $256, %rdx
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jb L(less_256bytes)
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vmovups %zmm2, (%rdi)
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vmovups %zmm2, 0x40(%rdi)
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vmovups %zmm2, 0x80(%rdi)
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vmovups %zmm2, 0xC0(%rdi)
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vmovups %zmm2, -0x100(%rsi)
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vmovups %zmm2, -0xC0(%rsi)
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vmovups %zmm2, -0x80(%rsi)
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vmovups %zmm2, -0x40(%rsi)
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ret
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L(less_256bytes):
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cmp $128, %dl
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jb L(less_128bytes)
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vmovups %zmm2, (%rdi)
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vmovups %zmm2, 0x40(%rdi)
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vmovups %zmm2, -0x80(%rsi)
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vmovups %zmm2, -0x40(%rsi)
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ret
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L(less_128bytes):
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cmp $64, %dl
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jb L(less_64bytes)
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vmovups %zmm2, (%rdi)
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vmovups %zmm2, -0x40(%rsi)
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ret
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L(less_64bytes):
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cmp $32, %dl
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jb L(less_32bytes)
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vmovdqu %ymm2, (%rdi)
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vmovdqu %ymm2, -0x20(%rsi)
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ret
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L(less_32bytes):
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vmovdqu %xmm0, (%rdi)
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vmovdqu %xmm0, -0x10(%rsi)
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ret
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L(less_16bytes):
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cmp $8, %dl
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jb L(less_8bytes)
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vmovq %xmm0, (%rdi)
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vmovq %xmm0, -0x08(%rsi)
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ret
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L(less_8bytes):
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vmovd %xmm0, %ecx
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cmp $4, %dl
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jb L(less_4bytes)
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mov %ecx, (%rdi)
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mov %ecx, -0x04(%rsi)
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ret
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L(less_4bytes):
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cmp $2, %dl
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jb L(less_2bytes)
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mov %cx, (%rdi)
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mov %cx, -0x02(%rsi)
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ret
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L(less_2bytes):
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cmp $1, %dl
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jb L(less_1bytes)
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mov %cl, (%rdi)
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L(less_1bytes):
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ret
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L(512bytesormore):
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mov __x86_shared_cache_size_half(%rip), %rcx
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cmp %rcx, %rdx
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ja L(preloop_large)
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cmp $1024, %rdx
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ja L(1024bytesormore)
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vmovups %zmm2, (%rdi)
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vmovups %zmm2, 0x40(%rdi)
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vmovups %zmm2, 0x80(%rdi)
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vmovups %zmm2, 0xC0(%rdi)
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vmovups %zmm2, 0x100(%rdi)
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vmovups %zmm2, 0x140(%rdi)
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vmovups %zmm2, 0x180(%rdi)
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vmovups %zmm2, 0x1C0(%rdi)
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vmovups %zmm2, -0x200(%rsi)
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vmovups %zmm2, -0x1C0(%rsi)
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vmovups %zmm2, -0x180(%rsi)
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vmovups %zmm2, -0x140(%rsi)
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vmovups %zmm2, -0x100(%rsi)
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vmovups %zmm2, -0xC0(%rsi)
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vmovups %zmm2, -0x80(%rsi)
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vmovups %zmm2, -0x40(%rsi)
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ret
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/* Align on 64 and loop with aligned stores. */
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L(1024bytesormore):
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sub $0x100, %rsi
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vmovups %zmm2, (%rax)
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and $-0x40, %rdi
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add $0x40, %rdi
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L(gobble_256bytes_loop):
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vmovaps %zmm2, (%rdi)
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vmovaps %zmm2, 0x40(%rdi)
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vmovaps %zmm2, 0x80(%rdi)
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vmovaps %zmm2, 0xC0(%rdi)
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add $0x100, %rdi
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cmp %rsi, %rdi
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jb L(gobble_256bytes_loop)
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vmovups %zmm2, (%rsi)
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vmovups %zmm2, 0x40(%rsi)
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vmovups %zmm2, 0x80(%rsi)
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vmovups %zmm2, 0xC0(%rsi)
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ret
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/* Align on 128 and loop with non-temporal stores. */
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L(preloop_large):
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and $-0x80, %rdi
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add $0x80, %rdi
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vmovups %zmm2, (%rax)
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vmovups %zmm2, 0x40(%rax)
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sub $0x200, %rsi
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L(gobble_512bytes_nt_loop):
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vmovntdq %zmm2, (%rdi)
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vmovntdq %zmm2, 0x40(%rdi)
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vmovntdq %zmm2, 0x80(%rdi)
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vmovntdq %zmm2, 0xC0(%rdi)
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vmovntdq %zmm2, 0x100(%rdi)
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vmovntdq %zmm2, 0x140(%rdi)
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vmovntdq %zmm2, 0x180(%rdi)
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vmovntdq %zmm2, 0x1C0(%rdi)
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add $0x200, %rdi
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cmp %rsi, %rdi
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jb L(gobble_512bytes_nt_loop)
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sfence
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vmovups %zmm2, (%rsi)
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vmovups %zmm2, 0x40(%rsi)
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vmovups %zmm2, 0x80(%rsi)
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vmovups %zmm2, 0xC0(%rsi)
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vmovups %zmm2, 0x100(%rsi)
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vmovups %zmm2, 0x140(%rsi)
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vmovups %zmm2, 0x180(%rsi)
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vmovups %zmm2, 0x1C0(%rsi)
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ret
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END (MEMSET)
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#endif
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