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Similar to other CPU feature checks, check if SSE is available with HAS_CPU_FEATURE. * sysdeps/i386/fpu/fclrexcpt.c (__feclearexcept): Use HAS_CPU_FEATURE to check for SSE. * sysdeps/i386/fpu/fedisblxcpt.c (fedisableexcept): Likewise. * sysdeps/i386/fpu/feenablxcpt.c (feenableexcept): Likewise. * sysdeps/i386/fpu/fegetenv.c (__fegetenv): Likewise. * sysdeps/i386/fpu/fegetmode.c (fegetmode): Likewise. * sysdeps/i386/fpu/feholdexcpt.c (__feholdexcept): Likewise. * sysdeps/i386/fpu/fesetenv.c (__fesetenv): Likewise. * sysdeps/i386/fpu/fesetmode.c (fesetmode): Likewise. * sysdeps/i386/fpu/fesetround.c (__fesetround): Likewise. * sysdeps/i386/fpu/feupdateenv.c (__feupdateenv): Likewise. * sysdeps/i386/fpu/fgetexcptflg.c (__fegetexceptflag): Likewise. * sysdeps/i386/fpu/fsetexcptflg.c (__fesetexceptflag): Likewise. * sysdeps/i386/fpu/ftestexcept.c (fetestexcept): Likewise. * sysdeps/i386/setfpucw.c (__setfpucw): Likewise. * sysdeps/x86/cpu-features.h (bit_cpu_SSE): New. (index_cpu_SSE): Likewise. (reg_SSE): Likewise.
50 lines
1.6 KiB
C
50 lines
1.6 KiB
C
/* Store current floating-point environment.
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Copyright (C) 1997-2017 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <fenv.h>
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#include <unistd.h>
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#include <ldsodefs.h>
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#include <dl-procinfo.h>
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int
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__fegetenv (fenv_t *envp)
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{
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__asm__ ("fnstenv %0" : "=m" (*envp));
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/* And load it right back since the processor changes the mask.
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Intel thought this opcode to be used in interrupt handlers which
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would block all exceptions. */
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__asm__ ("fldenv %0" : : "m" (*envp));
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if (HAS_CPU_FEATURE (SSE))
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__asm__ ("stmxcsr %0" : "=m" (envp->__eip));
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/* Success. */
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return 0;
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}
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#include <shlib-compat.h>
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#if SHLIB_COMPAT (libm, GLIBC_2_1, GLIBC_2_2)
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strong_alias (__fegetenv, __old_fegetenv)
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compat_symbol (libm, __old_fegetenv, fegetenv, GLIBC_2_1);
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#endif
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libm_hidden_def (__fegetenv)
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libm_hidden_ver (__fegetenv, fegetenv)
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versioned_symbol (libm, __fegetenv, fegetenv, GLIBC_2_2);
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