Fixed missing bitfieldInterleave definisions
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0b73091c7f
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@ -420,6 +420,62 @@ namespace glm
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return REG1 | (REG2 << 1);
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}
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template <>
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GLM_FUNC_QUALIFIER glm::uint32 bitfieldInterleave(glm::uint8 x, glm::uint8 y, glm::uint8 z)
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{
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glm::uint32 REG1(x);
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glm::uint32 REG2(y);
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glm::uint32 REG3(z);
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REG1 = ((REG1 << 16) | REG1) & glm::uint32(0x00FF0000FF0000FF);
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REG2 = ((REG2 << 16) | REG2) & glm::uint32(0x00FF0000FF0000FF);
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REG3 = ((REG3 << 16) | REG3) & glm::uint32(0x00FF0000FF0000FF);
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REG1 = ((REG1 << 8) | REG1) & glm::uint32(0xF00F00F00F00F00F);
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REG2 = ((REG2 << 8) | REG2) & glm::uint32(0xF00F00F00F00F00F);
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REG3 = ((REG3 << 8) | REG3) & glm::uint32(0xF00F00F00F00F00F);
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REG1 = ((REG1 << 4) | REG1) & glm::uint32(0x30C30C30C30C30C3);
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REG2 = ((REG2 << 4) | REG2) & glm::uint32(0x30C30C30C30C30C3);
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REG3 = ((REG3 << 4) | REG3) & glm::uint32(0x30C30C30C30C30C3);
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REG1 = ((REG1 << 2) | REG1) & glm::uint32(0x9249249249249249);
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REG2 = ((REG2 << 2) | REG2) & glm::uint32(0x9249249249249249);
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REG3 = ((REG3 << 2) | REG3) & glm::uint32(0x9249249249249249);
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return REG1 | (REG2 << 1) | (REG3 << 2);
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}
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template <>
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GLM_FUNC_QUALIFIER glm::uint64 bitfieldInterleave(glm::uint16 x, glm::uint16 y, glm::uint16 z)
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{
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glm::uint64 REG1(x);
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glm::uint64 REG2(y);
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glm::uint64 REG3(z);
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REG1 = ((REG1 << 32) | REG1) & glm::uint64(0xFFFF00000000FFFF);
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REG2 = ((REG2 << 32) | REG2) & glm::uint64(0xFFFF00000000FFFF);
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REG3 = ((REG3 << 32) | REG3) & glm::uint64(0xFFFF00000000FFFF);
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REG1 = ((REG1 << 16) | REG1) & glm::uint64(0x00FF0000FF0000FF);
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REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x00FF0000FF0000FF);
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REG3 = ((REG3 << 16) | REG3) & glm::uint64(0x00FF0000FF0000FF);
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REG1 = ((REG1 << 8) | REG1) & glm::uint64(0xF00F00F00F00F00F);
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REG2 = ((REG2 << 8) | REG2) & glm::uint64(0xF00F00F00F00F00F);
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REG3 = ((REG3 << 8) | REG3) & glm::uint64(0xF00F00F00F00F00F);
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REG1 = ((REG1 << 4) | REG1) & glm::uint64(0x30C30C30C30C30C3);
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REG2 = ((REG2 << 4) | REG2) & glm::uint64(0x30C30C30C30C30C3);
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REG3 = ((REG3 << 4) | REG3) & glm::uint64(0x30C30C30C30C30C3);
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REG1 = ((REG1 << 2) | REG1) & glm::uint64(0x9249249249249249);
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REG2 = ((REG2 << 2) | REG2) & glm::uint64(0x9249249249249249);
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REG3 = ((REG3 << 2) | REG3) & glm::uint64(0x9249249249249249);
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return REG1 | (REG2 << 1) | (REG3 << 2);
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}
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template <>
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GLM_FUNC_QUALIFIER glm::uint64 bitfieldInterleave(glm::uint32 x, glm::uint32 y, glm::uint32 z)
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{
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@ -450,6 +506,32 @@ namespace glm
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return REG1 | (REG2 << 1) | (REG3 << 2);
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}
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template <>
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GLM_FUNC_QUALIFIER glm::uint32 bitfieldInterleave(glm::uint8 x, glm::uint8 y, glm::uint8 z, glm::uint8 w)
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{
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glm::uint32 REG1(x);
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glm::uint32 REG2(y);
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glm::uint32 REG3(z);
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glm::uint32 REG4(w);
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REG1 = ((REG1 << 12) | REG1) & glm::uint32(0x000F000F000F000F);
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REG2 = ((REG2 << 12) | REG2) & glm::uint32(0x000F000F000F000F);
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REG3 = ((REG3 << 12) | REG3) & glm::uint32(0x000F000F000F000F);
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REG4 = ((REG4 << 12) | REG4) & glm::uint32(0x000F000F000F000F);
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REG1 = ((REG1 << 6) | REG1) & glm::uint32(0x0303030303030303);
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REG2 = ((REG2 << 6) | REG2) & glm::uint32(0x0303030303030303);
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REG3 = ((REG3 << 6) | REG3) & glm::uint32(0x0303030303030303);
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REG4 = ((REG4 << 6) | REG4) & glm::uint32(0x0303030303030303);
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REG1 = ((REG1 << 3) | REG1) & glm::uint32(0x1111111111111111);
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REG2 = ((REG2 << 3) | REG2) & glm::uint32(0x1111111111111111);
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REG3 = ((REG3 << 3) | REG3) & glm::uint32(0x1111111111111111);
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REG4 = ((REG4 << 3) | REG4) & glm::uint32(0x1111111111111111);
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return REG1 | (REG2 << 1) | (REG3 << 2) | (REG4 << 3);
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}
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template <>
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GLM_FUNC_QUALIFIER glm::uint64 bitfieldInterleave(glm::uint16 x, glm::uint16 y, glm::uint16 z, glm::uint16 w)
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{
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@ -47,6 +47,7 @@ GLM 0.9.5.3: 2014-0X-XX
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- Fixed CUDA issues (#169, #168, #183, #182)
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- Added support for all extensions but GTX_string_cast to CUDA
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- Fixed strict aliasing warnings in GCC 4.8.1 / Android NDK 9c (#152)
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- Fixed missing bitfieldInterleave definisions
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================================================================================
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GLM 0.9.5.2: 2014-02-08
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