mirror of
https://github.com/KhronosGroup/glslang
synced 2024-09-19 20:29:54 +00:00
7c3c50ea94
SPIR-V requires that any instruction using the result of an OpSampledImage instruction be in the same block as the OpSampledImage. This is hard to guarantee in code generation but easy to fix after the fact, by simply inserting a new OpSampledImage before the user of its result if needed, with the new instruction having the same operands as the original OpSampledImage. This change adds a new pass to spv::Builder::postProcess that does this. This might leave the original OpSampledImage instructions "orphaned" with no users of their result ID, but dead code elimination would take care of those further down the line.
550 lines
24 KiB
C++
550 lines
24 KiB
C++
//
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// Copyright (C) 2018 Google, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// Neither the name of 3Dlabs Inc. Ltd. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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// COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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// LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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// ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Post-processing for SPIR-V IR, in internal form, not standard binary form.
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//
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#include <cassert>
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#include <cstdlib>
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#include <unordered_map>
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#include <unordered_set>
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#include <algorithm>
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#include "SpvBuilder.h"
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#include "spirv.hpp"
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namespace spv {
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#include "GLSL.std.450.h"
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#include "GLSL.ext.KHR.h"
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#include "GLSL.ext.EXT.h"
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#include "GLSL.ext.AMD.h"
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#include "GLSL.ext.NV.h"
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#include "GLSL.ext.ARM.h"
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#include "GLSL.ext.QCOM.h"
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}
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namespace spv {
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// Hook to visit each operand type and result type of an instruction.
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// Will be called multiple times for one instruction, once for each typed
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// operand and the result.
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void Builder::postProcessType(const Instruction& inst, Id typeId)
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{
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// Characterize the type being questioned
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Id basicTypeOp = getMostBasicTypeClass(typeId);
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int width = 0;
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if (basicTypeOp == OpTypeFloat || basicTypeOp == OpTypeInt)
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width = getScalarTypeWidth(typeId);
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// Do opcode-specific checks
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switch (inst.getOpCode()) {
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case OpLoad:
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case OpStore:
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if (basicTypeOp == OpTypeStruct) {
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if (containsType(typeId, OpTypeInt, 8))
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addCapability(CapabilityInt8);
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if (containsType(typeId, OpTypeInt, 16))
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addCapability(CapabilityInt16);
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if (containsType(typeId, OpTypeFloat, 16))
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addCapability(CapabilityFloat16);
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} else {
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StorageClass storageClass = getStorageClass(inst.getIdOperand(0));
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if (width == 8) {
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switch (storageClass) {
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case StorageClassPhysicalStorageBufferEXT:
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case StorageClassUniform:
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case StorageClassStorageBuffer:
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case StorageClassPushConstant:
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break;
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default:
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addCapability(CapabilityInt8);
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break;
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}
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} else if (width == 16) {
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switch (storageClass) {
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case StorageClassPhysicalStorageBufferEXT:
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case StorageClassUniform:
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case StorageClassStorageBuffer:
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case StorageClassPushConstant:
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case StorageClassInput:
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case StorageClassOutput:
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break;
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default:
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if (basicTypeOp == OpTypeInt)
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addCapability(CapabilityInt16);
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if (basicTypeOp == OpTypeFloat)
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addCapability(CapabilityFloat16);
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break;
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}
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}
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}
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break;
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case OpCopyObject:
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break;
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case OpFConvert:
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case OpSConvert:
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case OpUConvert:
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// Look for any 8/16-bit storage capabilities. If there are none, assume that
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// the convert instruction requires the Float16/Int8/16 capability.
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if (containsType(typeId, OpTypeFloat, 16) || containsType(typeId, OpTypeInt, 16)) {
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bool foundStorage = false;
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for (auto it = capabilities.begin(); it != capabilities.end(); ++it) {
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spv::Capability cap = *it;
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if (cap == spv::CapabilityStorageInputOutput16 ||
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cap == spv::CapabilityStoragePushConstant16 ||
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cap == spv::CapabilityStorageUniformBufferBlock16 ||
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cap == spv::CapabilityStorageUniform16) {
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foundStorage = true;
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break;
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}
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}
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if (!foundStorage) {
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if (containsType(typeId, OpTypeFloat, 16))
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addCapability(CapabilityFloat16);
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if (containsType(typeId, OpTypeInt, 16))
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addCapability(CapabilityInt16);
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}
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}
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if (containsType(typeId, OpTypeInt, 8)) {
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bool foundStorage = false;
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for (auto it = capabilities.begin(); it != capabilities.end(); ++it) {
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spv::Capability cap = *it;
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if (cap == spv::CapabilityStoragePushConstant8 ||
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cap == spv::CapabilityUniformAndStorageBuffer8BitAccess ||
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cap == spv::CapabilityStorageBuffer8BitAccess) {
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foundStorage = true;
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break;
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}
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}
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if (!foundStorage) {
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addCapability(CapabilityInt8);
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}
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}
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break;
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case OpExtInst:
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switch (inst.getImmediateOperand(1)) {
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case GLSLstd450Frexp:
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case GLSLstd450FrexpStruct:
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if (getSpvVersion() < spv::Spv_1_3 && containsType(typeId, OpTypeInt, 16))
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addExtension(spv::E_SPV_AMD_gpu_shader_int16);
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break;
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case GLSLstd450InterpolateAtCentroid:
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case GLSLstd450InterpolateAtSample:
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case GLSLstd450InterpolateAtOffset:
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if (getSpvVersion() < spv::Spv_1_3 && containsType(typeId, OpTypeFloat, 16))
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addExtension(spv::E_SPV_AMD_gpu_shader_half_float);
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break;
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default:
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break;
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}
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break;
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case OpAccessChain:
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case OpPtrAccessChain:
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if (isPointerType(typeId))
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break;
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if (basicTypeOp == OpTypeInt) {
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if (width == 16)
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addCapability(CapabilityInt16);
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else if (width == 8)
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addCapability(CapabilityInt8);
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}
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break;
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default:
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if (basicTypeOp == OpTypeInt) {
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if (width == 16)
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addCapability(CapabilityInt16);
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else if (width == 8)
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addCapability(CapabilityInt8);
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else if (width == 64)
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addCapability(CapabilityInt64);
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} else if (basicTypeOp == OpTypeFloat) {
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if (width == 16)
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addCapability(CapabilityFloat16);
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else if (width == 64)
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addCapability(CapabilityFloat64);
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}
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break;
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}
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}
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// Called for each instruction that resides in a block.
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void Builder::postProcess(Instruction& inst)
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{
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// Add capabilities based simply on the opcode.
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switch (inst.getOpCode()) {
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case OpExtInst:
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switch (inst.getImmediateOperand(1)) {
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case GLSLstd450InterpolateAtCentroid:
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case GLSLstd450InterpolateAtSample:
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case GLSLstd450InterpolateAtOffset:
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addCapability(CapabilityInterpolationFunction);
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break;
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default:
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break;
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}
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break;
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case OpDPdxFine:
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case OpDPdyFine:
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case OpFwidthFine:
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case OpDPdxCoarse:
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case OpDPdyCoarse:
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case OpFwidthCoarse:
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addCapability(CapabilityDerivativeControl);
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break;
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case OpImageQueryLod:
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case OpImageQuerySize:
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case OpImageQuerySizeLod:
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case OpImageQuerySamples:
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case OpImageQueryLevels:
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addCapability(CapabilityImageQuery);
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break;
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case OpGroupNonUniformPartitionNV:
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addExtension(E_SPV_NV_shader_subgroup_partitioned);
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addCapability(CapabilityGroupNonUniformPartitionedNV);
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break;
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case OpLoad:
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case OpStore:
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{
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// For any load/store to a PhysicalStorageBufferEXT, walk the accesschain
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// index list to compute the misalignment. The pre-existing alignment value
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// (set via Builder::AccessChain::alignment) only accounts for the base of
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// the reference type and any scalar component selection in the accesschain,
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// and this function computes the rest from the SPIR-V Offset decorations.
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Instruction *accessChain = module.getInstruction(inst.getIdOperand(0));
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if (accessChain->getOpCode() == OpAccessChain) {
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Instruction *base = module.getInstruction(accessChain->getIdOperand(0));
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// Get the type of the base of the access chain. It must be a pointer type.
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Id typeId = base->getTypeId();
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Instruction *type = module.getInstruction(typeId);
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assert(type->getOpCode() == OpTypePointer);
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if (type->getImmediateOperand(0) != StorageClassPhysicalStorageBufferEXT) {
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break;
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}
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// Get the pointee type.
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typeId = type->getIdOperand(1);
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type = module.getInstruction(typeId);
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// Walk the index list for the access chain. For each index, find any
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// misalignment that can apply when accessing the member/element via
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// Offset/ArrayStride/MatrixStride decorations, and bitwise OR them all
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// together.
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int alignment = 0;
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for (int i = 1; i < accessChain->getNumOperands(); ++i) {
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Instruction *idx = module.getInstruction(accessChain->getIdOperand(i));
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if (type->getOpCode() == OpTypeStruct) {
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assert(idx->getOpCode() == OpConstant);
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unsigned int c = idx->getImmediateOperand(0);
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const auto function = [&](const std::unique_ptr<Instruction>& decoration) {
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if (decoration.get()->getOpCode() == OpMemberDecorate &&
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decoration.get()->getIdOperand(0) == typeId &&
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decoration.get()->getImmediateOperand(1) == c &&
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(decoration.get()->getImmediateOperand(2) == DecorationOffset ||
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decoration.get()->getImmediateOperand(2) == DecorationMatrixStride)) {
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alignment |= decoration.get()->getImmediateOperand(3);
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}
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};
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std::for_each(decorations.begin(), decorations.end(), function);
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// get the next member type
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typeId = type->getIdOperand(c);
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type = module.getInstruction(typeId);
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} else if (type->getOpCode() == OpTypeArray ||
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type->getOpCode() == OpTypeRuntimeArray) {
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const auto function = [&](const std::unique_ptr<Instruction>& decoration) {
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if (decoration.get()->getOpCode() == OpDecorate &&
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decoration.get()->getIdOperand(0) == typeId &&
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decoration.get()->getImmediateOperand(1) == DecorationArrayStride) {
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alignment |= decoration.get()->getImmediateOperand(2);
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}
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};
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std::for_each(decorations.begin(), decorations.end(), function);
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// Get the element type
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typeId = type->getIdOperand(0);
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type = module.getInstruction(typeId);
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} else {
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// Once we get to any non-aggregate type, we're done.
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break;
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}
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}
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assert(inst.getNumOperands() >= 3);
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unsigned int memoryAccess = inst.getImmediateOperand((inst.getOpCode() == OpStore) ? 2 : 1);
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assert(memoryAccess & MemoryAccessAlignedMask);
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static_cast<void>(memoryAccess);
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// Compute the index of the alignment operand.
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int alignmentIdx = 2;
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if (inst.getOpCode() == OpStore)
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alignmentIdx++;
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// Merge new and old (mis)alignment
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alignment |= inst.getImmediateOperand(alignmentIdx);
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// Pick the LSB
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alignment = alignment & ~(alignment & (alignment-1));
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// update the Aligned operand
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inst.setImmediateOperand(alignmentIdx, alignment);
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}
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break;
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}
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default:
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break;
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}
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// Checks based on type
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if (inst.getTypeId() != NoType)
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postProcessType(inst, inst.getTypeId());
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for (int op = 0; op < inst.getNumOperands(); ++op) {
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if (inst.isIdOperand(op)) {
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// In blocks, these are always result ids, but we are relying on
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// getTypeId() to return NoType for things like OpLabel.
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if (getTypeId(inst.getIdOperand(op)) != NoType)
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postProcessType(inst, getTypeId(inst.getIdOperand(op)));
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}
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}
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}
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// comment in header
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void Builder::postProcessCFG()
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{
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// reachableBlocks is the set of blockss reached via control flow, or which are
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// unreachable continue targert or unreachable merge.
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std::unordered_set<const Block*> reachableBlocks;
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std::unordered_map<Block*, Block*> headerForUnreachableContinue;
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std::unordered_set<Block*> unreachableMerges;
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std::unordered_set<Id> unreachableDefinitions;
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// Collect IDs defined in unreachable blocks. For each function, label the
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// reachable blocks first. Then for each unreachable block, collect the
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// result IDs of the instructions in it.
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for (auto fi = module.getFunctions().cbegin(); fi != module.getFunctions().cend(); fi++) {
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Function* f = *fi;
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Block* entry = f->getEntryBlock();
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inReadableOrder(entry,
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[&reachableBlocks, &unreachableMerges, &headerForUnreachableContinue]
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(Block* b, ReachReason why, Block* header) {
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reachableBlocks.insert(b);
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if (why == ReachDeadContinue) headerForUnreachableContinue[b] = header;
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if (why == ReachDeadMerge) unreachableMerges.insert(b);
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});
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for (auto bi = f->getBlocks().cbegin(); bi != f->getBlocks().cend(); bi++) {
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Block* b = *bi;
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if (unreachableMerges.count(b) != 0 || headerForUnreachableContinue.count(b) != 0) {
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auto ii = b->getInstructions().cbegin();
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++ii; // Keep potential decorations on the label.
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for (; ii != b->getInstructions().cend(); ++ii)
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unreachableDefinitions.insert(ii->get()->getResultId());
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} else if (reachableBlocks.count(b) == 0) {
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// The normal case for unreachable code. All definitions are considered dead.
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for (auto ii = b->getInstructions().cbegin(); ii != b->getInstructions().cend(); ++ii)
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unreachableDefinitions.insert(ii->get()->getResultId());
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}
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}
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}
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// Modify unreachable merge blocks and unreachable continue targets.
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// Delete their contents.
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for (auto mergeIter = unreachableMerges.begin(); mergeIter != unreachableMerges.end(); ++mergeIter) {
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(*mergeIter)->rewriteAsCanonicalUnreachableMerge();
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}
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for (auto continueIter = headerForUnreachableContinue.begin();
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continueIter != headerForUnreachableContinue.end();
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++continueIter) {
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Block* continue_target = continueIter->first;
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Block* header = continueIter->second;
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continue_target->rewriteAsCanonicalUnreachableContinue(header);
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}
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// Remove unneeded decorations, for unreachable instructions
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decorations.erase(std::remove_if(decorations.begin(), decorations.end(),
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[&unreachableDefinitions](std::unique_ptr<Instruction>& I) -> bool {
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Id decoration_id = I.get()->getIdOperand(0);
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return unreachableDefinitions.count(decoration_id) != 0;
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}),
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decorations.end());
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}
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// comment in header
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void Builder::postProcessFeatures() {
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// Add per-instruction capabilities, extensions, etc.,
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// Look for any 8/16 bit type in physical storage buffer class, and set the
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// appropriate capability. This happens in createSpvVariable for other storage
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// classes, but there isn't always a variable for physical storage buffer.
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for (int t = 0; t < (int)groupedTypes[OpTypePointer].size(); ++t) {
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Instruction* type = groupedTypes[OpTypePointer][t];
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if (type->getImmediateOperand(0) == (unsigned)StorageClassPhysicalStorageBufferEXT) {
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if (containsType(type->getIdOperand(1), OpTypeInt, 8)) {
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addIncorporatedExtension(spv::E_SPV_KHR_8bit_storage, spv::Spv_1_5);
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addCapability(spv::CapabilityStorageBuffer8BitAccess);
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}
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if (containsType(type->getIdOperand(1), OpTypeInt, 16) ||
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containsType(type->getIdOperand(1), OpTypeFloat, 16)) {
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addIncorporatedExtension(spv::E_SPV_KHR_16bit_storage, spv::Spv_1_3);
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addCapability(spv::CapabilityStorageBuffer16BitAccess);
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}
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}
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}
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// process all block-contained instructions
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for (auto fi = module.getFunctions().cbegin(); fi != module.getFunctions().cend(); fi++) {
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Function* f = *fi;
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for (auto bi = f->getBlocks().cbegin(); bi != f->getBlocks().cend(); bi++) {
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Block* b = *bi;
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for (auto ii = b->getInstructions().cbegin(); ii != b->getInstructions().cend(); ii++)
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postProcess(*ii->get());
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// For all local variables that contain pointers to PhysicalStorageBufferEXT, check whether
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// there is an existing restrict/aliased decoration. If we don't find one, add Aliased as the
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// default.
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for (auto vi = b->getLocalVariables().cbegin(); vi != b->getLocalVariables().cend(); vi++) {
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const Instruction& inst = *vi->get();
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Id resultId = inst.getResultId();
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if (containsPhysicalStorageBufferOrArray(getDerefTypeId(resultId))) {
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bool foundDecoration = false;
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const auto function = [&](const std::unique_ptr<Instruction>& decoration) {
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if (decoration.get()->getIdOperand(0) == resultId &&
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decoration.get()->getOpCode() == OpDecorate &&
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(decoration.get()->getImmediateOperand(1) == spv::DecorationAliasedPointerEXT ||
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decoration.get()->getImmediateOperand(1) == spv::DecorationRestrictPointerEXT)) {
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foundDecoration = true;
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}
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};
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std::for_each(decorations.begin(), decorations.end(), function);
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if (!foundDecoration) {
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addDecoration(resultId, spv::DecorationAliasedPointerEXT);
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}
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}
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}
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}
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}
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// If any Vulkan memory model-specific functionality is used, update the
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// OpMemoryModel to match.
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if (capabilities.find(spv::CapabilityVulkanMemoryModelKHR) != capabilities.end()) {
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memoryModel = spv::MemoryModelVulkanKHR;
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addIncorporatedExtension(spv::E_SPV_KHR_vulkan_memory_model, spv::Spv_1_5);
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}
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// Add Aliased decoration if there's more than one Workgroup Block variable.
|
|
if (capabilities.find(spv::CapabilityWorkgroupMemoryExplicitLayoutKHR) != capabilities.end()) {
|
|
assert(entryPoints.size() == 1);
|
|
auto &ep = entryPoints[0];
|
|
|
|
std::vector<Id> workgroup_variables;
|
|
for (int i = 0; i < (int)ep->getNumOperands(); i++) {
|
|
if (!ep->isIdOperand(i))
|
|
continue;
|
|
|
|
const Id id = ep->getIdOperand(i);
|
|
const Instruction *instr = module.getInstruction(id);
|
|
if (instr->getOpCode() != spv::OpVariable)
|
|
continue;
|
|
|
|
if (instr->getImmediateOperand(0) == spv::StorageClassWorkgroup)
|
|
workgroup_variables.push_back(id);
|
|
}
|
|
|
|
if (workgroup_variables.size() > 1) {
|
|
for (size_t i = 0; i < workgroup_variables.size(); i++)
|
|
addDecoration(workgroup_variables[i], spv::DecorationAliased);
|
|
}
|
|
}
|
|
}
|
|
|
|
// SPIR-V requires that any instruction consuming the result of an OpSampledImage
|
|
// be in the same block as the OpSampledImage instruction. This pass goes finds
|
|
// uses of OpSampledImage where that is not the case and duplicates the
|
|
// OpSampledImage to be immediately before the instruction that consumes it.
|
|
// The old OpSampledImage is left in place, potentially with no users.
|
|
void Builder::postProcessSamplers()
|
|
{
|
|
// first, find all OpSampledImage instructions and store them in a map.
|
|
std::map<Id, Instruction*> sampledImageInstrs;
|
|
for (auto f: module.getFunctions()) {
|
|
for (auto b: f->getBlocks()) {
|
|
for (auto &i: b->getInstructions()) {
|
|
if (i->getOpCode() == spv::OpSampledImage) {
|
|
sampledImageInstrs[i->getResultId()] = i.get();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
// next find all uses of the given ids and rewrite them if needed.
|
|
for (auto f: module.getFunctions()) {
|
|
for (auto b: f->getBlocks()) {
|
|
auto &instrs = b->getInstructions();
|
|
for (size_t idx = 0; idx < instrs.size(); idx++) {
|
|
Instruction *i = instrs[idx].get();
|
|
for (int opnum = 0; opnum < i->getNumOperands(); opnum++) {
|
|
// Is this operand of the current instruction the result of an OpSampledImage?
|
|
if (i->isIdOperand(opnum) &&
|
|
sampledImageInstrs.count(i->getIdOperand(opnum)))
|
|
{
|
|
Instruction *opSampImg = sampledImageInstrs[i->getIdOperand(opnum)];
|
|
if (i->getBlock() != opSampImg->getBlock()) {
|
|
Instruction *newInstr = new Instruction(getUniqueId(),
|
|
opSampImg->getTypeId(),
|
|
spv::OpSampledImage);
|
|
newInstr->addIdOperand(opSampImg->getIdOperand(0));
|
|
newInstr->addIdOperand(opSampImg->getIdOperand(1));
|
|
newInstr->setBlock(b);
|
|
|
|
// rewrite the user of the OpSampledImage to use the new instruction.
|
|
i->setIdOperand(opnum, newInstr->getResultId());
|
|
// insert the new OpSampledImage right before the current instruction.
|
|
instrs.insert(instrs.begin() + idx,
|
|
std::unique_ptr<Instruction>(newInstr));
|
|
idx++;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// comment in header
|
|
void Builder::postProcess(bool compileOnly)
|
|
{
|
|
// postProcessCFG needs an entrypoint to determine what is reachable, but if we are not creating an "executable" shader, we don't have an entrypoint
|
|
if (!compileOnly)
|
|
postProcessCFG();
|
|
|
|
postProcessFeatures();
|
|
postProcessSamplers();
|
|
}
|
|
|
|
}; // end spv namespace
|