AuroraMiddleware/mimalloc
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Support ARM/Aarch64 TLS register fastpath

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Tested with Ubuntu Linux 18.04 LTS running on Marvell/Cavium ThunderX,
which consists of Armv8 based processors.
This commit is contained in:
Jim Huang 2019-06-23 16:25:33 +08:00 committed by Jim Huang
parent 06f8da4218
commit 3841b32f9d
1 changed files with 7 additions and 2 deletions
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9
include/mimalloc-internal.h
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@ -291,7 +291,8 @@ static inline uintptr_t _mi_thread_id() mi_attr_noexcept {
// Windows: works on Intel and ARM in both 32- and 64-bit // Windows: works on Intel and ARM in both 32- and 64-bit
return (uintptr_t)NtCurrentTeb(); return (uintptr_t)NtCurrentTeb();
} }
#elif (defined(__GNUC__) || defined(__clang__)) && (defined(__x86_64__) || defined(__i386__)) #elif (defined(__GNUC__) || defined(__clang__)) && \
(defined(__x86_64__) || defined(__i386__) || defined(__arm__) || defined(__aarch64__))
// TLS register on x86 is in the FS or GS register // TLS register on x86 is in the FS or GS register
// see: https://akkadia.org/drepper/tls.pdf // see: https://akkadia.org/drepper/tls.pdf
static inline uintptr_t _mi_thread_id() mi_attr_noexcept { static inline uintptr_t _mi_thread_id() mi_attr_noexcept {
@ -300,8 +301,12 @@ static inline uintptr_t _mi_thread_id() mi_attr_noexcept {
__asm__("movl %%gs:0, %0" : "=r" (tid) : : ); // 32-bit always uses GS __asm__("movl %%gs:0, %0" : "=r" (tid) : : ); // 32-bit always uses GS
#elif defined(__MACH__) #elif defined(__MACH__)
__asm__("movq %%gs:0, %0" : "=r" (tid) : : ); // x86_64 MacOSX uses GS __asm__("movq %%gs:0, %0" : "=r" (tid) : : ); // x86_64 MacOSX uses GS
#else #elif defined(__x86_64__)
__asm__("movq %%fs:0, %0" : "=r" (tid) : : ); // x86_64 Linux, BSD uses FS __asm__("movq %%fs:0, %0" : "=r" (tid) : : ); // x86_64 Linux, BSD uses FS
#elif defined(__arm__)
asm volatile ("mrc p15, 0, %0, c13, c0, 3" : "=r" (tid));
#elif defined(__aarch64__)
asm volatile ("mrs %0, tpidr_el0" : "=r" (tid));
#endif #endif
return tid; return tid;
} }