Add support for the TILE-Gx processor family.
This commit is contained in:
parent
5446deaea7
commit
e85de03b81
@ -42,6 +42,7 @@ nobase_include_HEADERS = \
|
||||
google/protobuf/stubs/atomicops.h \
|
||||
google/protobuf/stubs/atomicops_internals_aix.h \
|
||||
google/protobuf/stubs/atomicops_internals_arm64_gcc.h \
|
||||
google/protobuf/stubs/atomicops_internals_tile_gcc.h \
|
||||
google/protobuf/stubs/atomicops_internals_arm_gcc.h \
|
||||
google/protobuf/stubs/atomicops_internals_arm_qnx.h \
|
||||
google/protobuf/stubs/atomicops_internals_atomicword_compat.h \
|
||||
|
@ -207,6 +207,8 @@ GOOGLE_PROTOBUF_ATOMICOPS_ERROR
|
||||
#include <google/protobuf/stubs/atomicops_internals_arm64_gcc.h>
|
||||
#elif defined(GOOGLE_PROTOBUF_ARCH_ARM_QNX)
|
||||
#include <google/protobuf/stubs/atomicops_internals_arm_qnx.h>
|
||||
#elif defined(GOOGLE_PROTOBUF_ARCH_TILE)
|
||||
#include <google/protobuf/stubs/atomicops_internals_tile_gcc.h>
|
||||
#elif defined(GOOGLE_PROTOBUF_ARCH_MIPS) || defined(GOOGLE_PROTOBUF_ARCH_MIPS64)
|
||||
#include <google/protobuf/stubs/atomicops_internals_mips_gcc.h>
|
||||
#elif defined(__native_client__)
|
||||
|
77
src/google/protobuf/stubs/atomicops_internals_tile_gcc.h
Normal file
77
src/google/protobuf/stubs/atomicops_internals_tile_gcc.h
Normal file
@ -0,0 +1,77 @@
|
||||
#ifndef GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_ARM64_GCC_H_
|
||||
#define GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_ARM64_GCC_H_
|
||||
|
||||
namespace google {
|
||||
namespace protobuf {
|
||||
namespace internal {
|
||||
|
||||
inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
|
||||
asm volatile ("st4 %0, %1"
|
||||
: "=r" (*ptr)
|
||||
: "m" (value));
|
||||
}
|
||||
|
||||
inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
|
||||
Atomic32 dest;
|
||||
asm volatile ("ld4s %0, %1"
|
||||
: "=r" (dest)
|
||||
: "m" (*ptr));
|
||||
return dest;
|
||||
}
|
||||
|
||||
inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
|
||||
asm volatile ("st %0, %1"
|
||||
: "=r" (*ptr)
|
||||
: "m" (value));
|
||||
}
|
||||
|
||||
inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
|
||||
Atomic64 dest;
|
||||
asm volatile ("ld %0, %1"
|
||||
: "=r" (dest)
|
||||
: "m" (*ptr));
|
||||
return dest;
|
||||
}
|
||||
|
||||
inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
|
||||
return NoBarrier_Load(ptr);
|
||||
}
|
||||
|
||||
inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
|
||||
NoBarrier_Store(ptr, value);
|
||||
}
|
||||
|
||||
inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
|
||||
Atomic64 old_value,
|
||||
Atomic64 new_value) {
|
||||
Atomic64 tmp;
|
||||
asm volatile ("mtspr CMPEXCH_VALUE, %3\n\t"
|
||||
"cmpexch %0, %1, %2"
|
||||
: "=r" (tmp), "=m" (*ptr)
|
||||
: "r" (new_value), "r" (old_value));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
|
||||
Atomic64 new_value) {
|
||||
Atomic64 old_value;
|
||||
asm volatile ("exch %0, %1, %2"
|
||||
: "=r" (old_value), "=m" (*ptr)
|
||||
: "r" (new_value));
|
||||
return old_value;
|
||||
}
|
||||
|
||||
inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
|
||||
Atomic64 value) {
|
||||
Atomic64 dest;
|
||||
asm volatile ("fetchadd %0, %1, %2"
|
||||
: "=r" (dest), "=m" (*ptr)
|
||||
: "r" (value));
|
||||
return *ptr;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
@ -52,6 +52,9 @@
|
||||
#elif defined(__ARMEL__)
|
||||
#define GOOGLE_PROTOBUF_ARCH_ARM 1
|
||||
#define GOOGLE_PROTOBUF_ARCH_32_BIT 1
|
||||
#elif defined(__tile__)
|
||||
#define GOOGLE_PROTOBUF_ARCH_TILE 1
|
||||
#define GOOGLE_PROTOBUF_ARCH_64_BIT 1
|
||||
#elif defined(__aarch64__)
|
||||
#define GOOGLE_PROTOBUF_ARCH_AARCH64 1
|
||||
#define GOOGLE_PROTOBUF_ARCH_64_BIT 1
|
||||
|
Loading…
Reference in New Issue
Block a user