Add support for the TILE-Gx processor family.
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@ -42,6 +42,7 @@ nobase_include_HEADERS = \
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google/protobuf/stubs/atomicops.h \
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google/protobuf/stubs/atomicops.h \
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google/protobuf/stubs/atomicops_internals_aix.h \
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google/protobuf/stubs/atomicops_internals_aix.h \
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google/protobuf/stubs/atomicops_internals_arm64_gcc.h \
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google/protobuf/stubs/atomicops_internals_arm64_gcc.h \
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google/protobuf/stubs/atomicops_internals_tile_gcc.h \
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google/protobuf/stubs/atomicops_internals_arm_gcc.h \
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google/protobuf/stubs/atomicops_internals_arm_gcc.h \
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google/protobuf/stubs/atomicops_internals_arm_qnx.h \
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google/protobuf/stubs/atomicops_internals_arm_qnx.h \
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google/protobuf/stubs/atomicops_internals_atomicword_compat.h \
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google/protobuf/stubs/atomicops_internals_atomicword_compat.h \
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@ -207,6 +207,8 @@ GOOGLE_PROTOBUF_ATOMICOPS_ERROR
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#include <google/protobuf/stubs/atomicops_internals_arm64_gcc.h>
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#include <google/protobuf/stubs/atomicops_internals_arm64_gcc.h>
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#elif defined(GOOGLE_PROTOBUF_ARCH_ARM_QNX)
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#elif defined(GOOGLE_PROTOBUF_ARCH_ARM_QNX)
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#include <google/protobuf/stubs/atomicops_internals_arm_qnx.h>
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#include <google/protobuf/stubs/atomicops_internals_arm_qnx.h>
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#elif defined(GOOGLE_PROTOBUF_ARCH_TILE)
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#include <google/protobuf/stubs/atomicops_internals_tile_gcc.h>
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#elif defined(GOOGLE_PROTOBUF_ARCH_MIPS) || defined(GOOGLE_PROTOBUF_ARCH_MIPS64)
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#elif defined(GOOGLE_PROTOBUF_ARCH_MIPS) || defined(GOOGLE_PROTOBUF_ARCH_MIPS64)
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#include <google/protobuf/stubs/atomicops_internals_mips_gcc.h>
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#include <google/protobuf/stubs/atomicops_internals_mips_gcc.h>
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#elif defined(__native_client__)
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#elif defined(__native_client__)
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77
src/google/protobuf/stubs/atomicops_internals_tile_gcc.h
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src/google/protobuf/stubs/atomicops_internals_tile_gcc.h
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@ -0,0 +1,77 @@
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#ifndef GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_ARM64_GCC_H_
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#define GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_ARM64_GCC_H_
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namespace google {
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namespace protobuf {
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namespace internal {
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inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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asm volatile ("st4 %0, %1"
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: "=r" (*ptr)
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: "m" (value));
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}
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inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
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Atomic32 dest;
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asm volatile ("ld4s %0, %1"
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: "=r" (dest)
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: "m" (*ptr));
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return dest;
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}
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inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
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asm volatile ("st %0, %1"
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: "=r" (*ptr)
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: "m" (value));
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}
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inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
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Atomic64 dest;
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asm volatile ("ld %0, %1"
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: "=r" (dest)
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: "m" (*ptr));
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return dest;
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}
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inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
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return NoBarrier_Load(ptr);
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}
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inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
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NoBarrier_Store(ptr, value);
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}
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inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 tmp;
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asm volatile ("mtspr CMPEXCH_VALUE, %3\n\t"
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"cmpexch %0, %1, %2"
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: "=r" (tmp), "=m" (*ptr)
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: "r" (new_value), "r" (old_value));
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return tmp;
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}
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inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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Atomic64 old_value;
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asm volatile ("exch %0, %1, %2"
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: "=r" (old_value), "=m" (*ptr)
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: "r" (new_value));
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return old_value;
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}
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inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 value) {
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Atomic64 dest;
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asm volatile ("fetchadd %0, %1, %2"
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: "=r" (dest), "=m" (*ptr)
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: "r" (value));
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return *ptr;
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}
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}
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}
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}
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#endif
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@ -52,6 +52,9 @@
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#elif defined(__ARMEL__)
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#elif defined(__ARMEL__)
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#define GOOGLE_PROTOBUF_ARCH_ARM 1
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#define GOOGLE_PROTOBUF_ARCH_ARM 1
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#define GOOGLE_PROTOBUF_ARCH_32_BIT 1
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#define GOOGLE_PROTOBUF_ARCH_32_BIT 1
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#elif defined(__tile__)
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#define GOOGLE_PROTOBUF_ARCH_TILE 1
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#define GOOGLE_PROTOBUF_ARCH_64_BIT 1
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#elif defined(__aarch64__)
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#elif defined(__aarch64__)
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#define GOOGLE_PROTOBUF_ARCH_AARCH64 1
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#define GOOGLE_PROTOBUF_ARCH_AARCH64 1
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#define GOOGLE_PROTOBUF_ARCH_64_BIT 1
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#define GOOGLE_PROTOBUF_ARCH_64_BIT 1
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