qsimd: add support for new x86 CPU features
This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI,
AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These
features were found in the "Intel® Architecture Instruction Set
Extensions and Future Features" manual, revision 30. This commit also
adds support for RDPID (already in the main manual) and the Control-flow
Enforcement Technology, which appears in a separate Intel paper.
This new support was done by adding a new generator script so we don't
have to maintain two tables in sync, one in qsimd.cpp with the feature
names, and the other in qsimd_p.h.
Since we now need a lot more bits, it's no longer worth keeping the two
halves of the qt_cpu_features variable mostly similar to the main two
CPUID results. This commit goes back to keeping things in order, like we
used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6)
At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ,
AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI.
Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96
Reviewed-by: Edward Welbourne <edward.welbourne@qt.io>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
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#!/usr/bin/env perl
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#############################################################################
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##
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## Copyright (C) 2018 Intel Corporation.
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## Contact: https://www.qt.io/licensing/
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##
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## This file is part of the build configuration tools of the Qt Toolkit.
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##
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## $QT_BEGIN_LICENSE:MIT$
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## Permission is hereby granted, free of charge, to any person obtaining a copy
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## of this software and associated documentation files (the "Software"), to deal
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## in the Software without restriction, including without limitation the rights
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## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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## copies of the Software, and to permit persons to whom the Software is
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## furnished to do so, subject to the following conditions:
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##
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## The above copyright notice and this permission notice shall be included in
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## all copies or substantial portions of the Software.
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##
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## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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## THE SOFTWARE.
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## $QT_END_LICENSE$
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##
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#############################################################################
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use strict;
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$\ = "\n";
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$/ = "\n";
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my %leaves = (
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Leaf1EDX => "CPUID Leaf 1, EDX",
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Leaf1ECX => "CPUID Leaf 1, ECX",
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Leaf7_0EBX => "CPUID Leaf 7, Sub-leaf 0, EBX",
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Leaf7_0ECX => "CPUID Leaf 7, Sub-leaf 0, ECX",
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Leaf7_0EDX => "CPUID Leaf 7, Sub-leaf 0, EDX",
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);
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my @leafNames = sort keys %leaves;
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# Read data from stdin
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my $i = 1;
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my @features;
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while (<STDIN>) {
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s/#.*$//;
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chomp;
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next if $_ eq "";
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my ($name, $function, $bit, $depends) = split /\s+/;
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die("Unknown CPUID function \"$function\"")
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unless grep $function, @leafNames;
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my $id = uc($name);
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$id =~ s/[^A-Z0-9_]/_/g;
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push @features,
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{ name => $name, depends => $depends, id => $id, bit => $bit, leaf => $function };
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++$i;
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}
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if (my $h = shift @ARGV) {
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open HEADER, ">", $h;
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select HEADER;
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}
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# Print the qsimd_x86_p.h output
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print q{// This is a generated file. DO NOT EDIT.
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// Please see util/x86simdgen/generate.pl";
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#ifndef QSIMD_P_H
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# error "Please include <private/qsimd_p.h> instead"
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#endif
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#ifndef QSIMD_X86_P_H
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#define QSIMD_X86_P_H
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#include "qsimd_p.h"
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//
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// W A R N I N G
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// -------------
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//
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// This file is not part of the Qt API. It exists purely as an
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// implementation detail. This header file may change from version to
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// version without notice, or even be removed.
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//
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// We mean it.
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//
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QT_BEGIN_NAMESPACE
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2018-06-25 23:27:48 +00:00
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// used only to indicate that the CPU detection was initialized
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#define QSimdInitialized (Q_UINT64_C(1) << 0)};
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qsimd: add support for new x86 CPU features
This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI,
AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These
features were found in the "Intel® Architecture Instruction Set
Extensions and Future Features" manual, revision 30. This commit also
adds support for RDPID (already in the main manual) and the Control-flow
Enforcement Technology, which appears in a separate Intel paper.
This new support was done by adding a new generator script so we don't
have to maintain two tables in sync, one in qsimd.cpp with the feature
names, and the other in qsimd_p.h.
Since we now need a lot more bits, it's no longer worth keeping the two
halves of the qt_cpu_features variable mostly similar to the main two
CPUID results. This commit goes back to keeping things in order, like we
used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6)
At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ,
AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI.
Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96
Reviewed-by: Edward Welbourne <edward.welbourne@qt.io>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
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# Print the enum
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my $lastleaf;
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for (my $i = 0; $i < scalar @features; ++$i) {
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my $feature = $features[$i];
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# Leaf header:
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2018-06-21 02:08:14 +00:00
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printf "\n// in %s:\n", $leaves{$feature->{leaf}}
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qsimd: add support for new x86 CPU features
This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI,
AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These
features were found in the "Intel® Architecture Instruction Set
Extensions and Future Features" manual, revision 30. This commit also
adds support for RDPID (already in the main manual) and the Control-flow
Enforcement Technology, which appears in a separate Intel paper.
This new support was done by adding a new generator script so we don't
have to maintain two tables in sync, one in qsimd.cpp with the feature
names, and the other in qsimd_p.h.
Since we now need a lot more bits, it's no longer worth keeping the two
halves of the qt_cpu_features variable mostly similar to the main two
CPUID results. This commit goes back to keeping things in order, like we
used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6)
At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ,
AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI.
Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96
Reviewed-by: Edward Welbourne <edward.welbourne@qt.io>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
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if $feature->{leaf} ne $lastleaf;
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$lastleaf = $feature->{leaf};
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# Feature
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2018-06-25 23:27:48 +00:00
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printf "#define CpuFeature%-33s (Q_UINT64_C(1) << %d)\n", $feature->{id}, $i + 1;
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# Feature string names for Clang and GCC
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my $str = $feature->{name};
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$str .= ",$feature->{depends}" if defined($feature->{depends});
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printf "#define QT_FUNCTION_TARGET_STRING_%-17s \"%s\"\n",
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$feature->{id}, $str;
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qsimd: add support for new x86 CPU features
This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI,
AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These
features were found in the "Intel® Architecture Instruction Set
Extensions and Future Features" manual, revision 30. This commit also
adds support for RDPID (already in the main manual) and the Control-flow
Enforcement Technology, which appears in a separate Intel paper.
This new support was done by adding a new generator script so we don't
have to maintain two tables in sync, one in qsimd.cpp with the feature
names, and the other in qsimd_p.h.
Since we now need a lot more bits, it's no longer worth keeping the two
halves of the qt_cpu_features variable mostly similar to the main two
CPUID results. This commit goes back to keeping things in order, like we
used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6)
At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ,
AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI.
Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96
Reviewed-by: Edward Welbourne <edward.welbourne@qt.io>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
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}
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print q{
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static const quint64 qCompilerCpuFeatures = 0};
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# And print the compiler-enabled features part:
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2018-06-21 02:08:14 +00:00
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for (my $i = 0; $i < scalar @features; ++$i) {
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my $feature = $features[$i];
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qsimd: add support for new x86 CPU features
This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI,
AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These
features were found in the "Intel® Architecture Instruction Set
Extensions and Future Features" manual, revision 30. This commit also
adds support for RDPID (already in the main manual) and the Control-flow
Enforcement Technology, which appears in a separate Intel paper.
This new support was done by adding a new generator script so we don't
have to maintain two tables in sync, one in qsimd.cpp with the feature
names, and the other in qsimd_p.h.
Since we now need a lot more bits, it's no longer worth keeping the two
halves of the qt_cpu_features variable mostly similar to the main two
CPUID results. This commit goes back to keeping things in order, like we
used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6)
At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ,
AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI.
Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96
Reviewed-by: Edward Welbourne <edward.welbourne@qt.io>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
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printf
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"#ifdef __%s__\n" .
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2018-06-25 23:27:48 +00:00
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" | CpuFeature%s\n" .
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qsimd: add support for new x86 CPU features
This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI,
AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These
features were found in the "Intel® Architecture Instruction Set
Extensions and Future Features" manual, revision 30. This commit also
adds support for RDPID (already in the main manual) and the Control-flow
Enforcement Technology, which appears in a separate Intel paper.
This new support was done by adding a new generator script so we don't
have to maintain two tables in sync, one in qsimd.cpp with the feature
names, and the other in qsimd_p.h.
Since we now need a lot more bits, it's no longer worth keeping the two
halves of the qt_cpu_features variable mostly similar to the main two
CPUID results. This commit goes back to keeping things in order, like we
used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6)
At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ,
AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI.
Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96
Reviewed-by: Edward Welbourne <edward.welbourne@qt.io>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
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"#endif\n",
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2018-06-25 23:27:48 +00:00
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$feature->{id}, $feature->{id};
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qsimd: add support for new x86 CPU features
This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI,
AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These
features were found in the "Intel® Architecture Instruction Set
Extensions and Future Features" manual, revision 30. This commit also
adds support for RDPID (already in the main manual) and the Control-flow
Enforcement Technology, which appears in a separate Intel paper.
This new support was done by adding a new generator script so we don't
have to maintain two tables in sync, one in qsimd.cpp with the feature
names, and the other in qsimd_p.h.
Since we now need a lot more bits, it's no longer worth keeping the two
halves of the qt_cpu_features variable mostly similar to the main two
CPUID results. This commit goes back to keeping things in order, like we
used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6)
At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ,
AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI.
Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96
Reviewed-by: Edward Welbourne <edward.welbourne@qt.io>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
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}
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print q{ ;
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QT_END_NAMESPACE
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#endif // QSIMD_X86_P_H
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};
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if (my $cpp = shift @ARGV) {
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open CPP, ">", $cpp;
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select CPP;
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} else {
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print q{
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---- cut here, paste the rest into qsimd_x86.cpp ---
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};
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};
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print "// This is a generated file. DO NOT EDIT.";
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print "// Please see util/x86simdgen/generate.pl";
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2018-06-21 02:08:14 +00:00
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print '#include "qsimd_p.h"';
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qsimd: add support for new x86 CPU features
This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI,
AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These
features were found in the "Intel® Architecture Instruction Set
Extensions and Future Features" manual, revision 30. This commit also
adds support for RDPID (already in the main manual) and the Control-flow
Enforcement Technology, which appears in a separate Intel paper.
This new support was done by adding a new generator script so we don't
have to maintain two tables in sync, one in qsimd.cpp with the feature
names, and the other in qsimd_p.h.
Since we now need a lot more bits, it's no longer worth keeping the two
halves of the qt_cpu_features variable mostly similar to the main two
CPUID results. This commit goes back to keeping things in order, like we
used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6)
At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ,
AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI.
Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96
Reviewed-by: Edward Welbourne <edward.welbourne@qt.io>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
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print "";
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# Now generate the string table and bit-location array
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my $offset = 0;
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my @offsets;
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print "static const char features_string[] =";
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for my $feature (@features) {
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print " \" $feature->{name}\\0\"";
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push @offsets, $offset;
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$offset += 2 + length($feature->{name});
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}
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print " \"\\0\";";
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# Print the string offset table
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printf "\nstatic const %s features_indices[] = {\n %3d",
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$offset > 255 ? "quint16" : "quint8", $offset;
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for (my $j = 0; $j < scalar @offsets; ++$j) {
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printf ",%s%3d",
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($j + 1) % 8 ? " " : "\n ", $offsets[$j];
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}
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print "\n};";
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# Print the locator enum and table
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print "\nenum X86CpuidLeaves {";
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map { print " $_," } @leafNames;
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print " X86CpuidMaxLeaf\n};";
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my $type = scalar %leaves > 8 ? "quint16" : "quint8";
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printf "\nstatic const %s x86_locators[] = {",
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$type, $type;
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my $lastname;
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for (my $j = 0; $j < scalar @features; ++$j) {
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my $feature = $features[$j];
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printf ", // %s", $lastname
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if defined($lastname);
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printf "\n %s*32 + %2d",
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$feature->{leaf}, $feature->{bit};
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$lastname = $feature->{name};
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}
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2018-06-21 02:08:14 +00:00
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printf qq{ // $lastname
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\};
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// List of AVX512 features (see detectProcessorFeatures())
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static const quint64 AllAVX512 = 0};
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# Print AVX512 features
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for (my $j = 0; $j < scalar @features; ++$j) {
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my $feature = $features[$j];
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$_ = $feature->{id};
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printf "\n | CpuFeature%s", $_ if /AVX512/;
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}
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print ";";
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