Add support for single-file multi-target intrinsics in Qt
GCC 4.9 now allows us to #include any and all intrinsics headers, not just the one for which we're compiling code, a behavior that ICC and MSVC have had for some time. With that, we're able to have the functions for different targets in the same source file. See the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/Function-Multiversioning.html This functionality is notified by the QT_COMPILER_SUPPORTS_HERE(XXX) macro, which indicates that all the intrinsics from QT_COMPILER_SUPPORTS_xxx are available and enabled. To complement, a QT_COMPILER_SUPPORTS(XXX) macro is also added. Unlike ICC and MSVC, GCC requires a special function attribute, which will also cause code optimization. That's the QT_FUNCTION_TARGET macro. Note: because of the absence of the target attribute, ICC and MSVC will not generate instructions with the VEX prefix unless they only exist with the VEX prefix or if -mavx / -arch:AVX are enabled. Change-Id: I0c1880c20324bd8e0fc68a863e36d1fa7755dff0 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@digia.com>
This commit is contained in:
Thiago Macieira
The Qt Project
parent
cb09e1e889
commit
689e8055f5
2
configure
vendored
2
configure
vendored
@ -6035,7 +6035,7 @@ for SUBARCH in SSE2 SSE3 SSSE3 SSE4_1 SSE4_2 AVX AVX2 \
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eval "VAL=\$CFG_$SUBARCH"
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case "$VAL" in
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yes)
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echo "#define QT_COMPILER_SUPPORTS_$SUBARCH" \
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echo "#define QT_COMPILER_SUPPORTS_$SUBARCH 1" \
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>>"$outpath/src/corelib/global/qconfig.h.new"
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;;
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esac
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@ -94,13 +94,14 @@ QT_BEGIN_NAMESPACE
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(for instance, gcc 4.4 does that even at -O0).
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*/
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#ifdef __SSE4_2__
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#if QT_COMPILER_SUPPORTS_HERE(SSE4_2)
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static inline bool hasFastCrc32()
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{
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return true;
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return qCpuHasFeature(SSE4_2);
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}
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template <typename Char>
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QT_FUNCTION_TARGET(SSE4_2)
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static uint crc32(const Char *ptr, size_t len, uint h)
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{
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// The CRC32 instructions from Nehalem calculate a 32-bit CRC32 checksum
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@ -50,6 +50,7 @@
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* They mean the compiler supports the necessary flags and the headers
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* for the x86 and ARM intrinsics:
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* - GCC: the -mXXX or march=YYY flag is necessary before #include
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* up to 4.8; GCC >= 4.9 can include unconditionally
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* - Intel CC: #include can happen unconditionally
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* - MSVC: #include can happen unconditionally
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* - RVCT: ???
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@ -60,25 +61,99 @@
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* up do define __AVX__ if the -arch:AVX option is passed on the command-line.
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*
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* Supported XXX are:
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* Flag | Arch | GCC | Intel CC | MSVC |
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* NEON | ARM | I & C | None | ? |
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* IWMMXT | ARM | I & C | None | I & C |
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* SSE2 | x86 | I & C | I & C | I & C |
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* SSE3 | x86 | I & C | I & C | I only |
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* SSSE3 | x86 | I & C | I & C | I only |
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* SSE4_1 | x86 | I & C | I & C | I only |
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* SSE4_2 | x86 | I & C | I & C | I only |
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* AVX | x86 | I & C | I & C | I & C |
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* AVX2 | x86 | I & C | I & C | I only |
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* Flag | Arch | GCC | Intel CC | MSVC |
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* ARM_NEON | ARM | I & C | None | ? |
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* IWMMXT | ARM | I & C | None | I & C |
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* SSE2 | x86 | I & C | I & C | I & C |
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* SSE3 | x86 | I & C | I & C | I only |
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* SSSE3 | x86 | I & C | I & C | I only |
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* SSE4_1 | x86 | I & C | I & C | I only |
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* SSE4_2 | x86 | I & C | I & C | I only |
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* AVX | x86 | I & C | I & C | I & C |
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* AVX2 | x86 | I & C | I & C | I only |
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* I = intrinsics; C = code generation
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*
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* Code can use the following constructs to determine compiler support & status:
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* - #ifdef __XXX__ (e.g: #ifdef __AVX__ or #ifdef __ARM_NEON__)
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* If this test passes, then the compiler is already generating code for that
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* given sub-architecture. The intrinsics for that sub-architecture are
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* #included and can be used without restriction or runtime check.
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*
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* - #if QT_COMPILER_SUPPORTS(XXX)
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* If this test passes, then the compiler is able to generate code for that
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* given sub-architecture in another translation unit, given the right set of
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* flags. Use of the intrinsics is not guaranteed. This is useful with
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* runtime detection (see below).
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*
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* - #if QT_COMPILER_SUPPORTS_HERE(XXX)
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* If this test passes, then the compiler is able to generate code for that
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* given sub-architecture in this translation unit, even if it is not doing
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* that now (it might be). Individual functions may be tagged with
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* QT_FUNCTION_TARGET(XXX) to cause the compiler to generate code for that
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* sub-arch. Only inside such functions is the use of the intrisics
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* guaranteed to work. This is useful with runtime detection (see below).
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*
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* Runtime detection of a CPU sub-architecture can be done with the
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* qCpuHasFeature(XXX) function. There are two strategies for generating
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* optimized code like that:
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*
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* 1) place the optimized code in a different translation unit (C or assembly
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* sources) and pass the correct flags to the compiler to enable support. Those
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* sources must not include qglobal.h, which means they cannot include this
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* file either. The dispatcher function would look like this:
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*
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* void foo()
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* {
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* #if QT_COMPILER_SUPPORTS(XXX)
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* if (qCpuHasFeature(XXX)) {
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* foo_optimized_xxx();
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* return;
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* }
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* #endif
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* foo_plain();
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* }
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*
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* 2) place the optimized code in a function tagged with QT_FUNCTION_TARGET and
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* surrounded by #if QT_COMPILER_SUPPORTS_HERE(XXX). That code can freely use
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* other Qt code. The dispatcher function would look like this:
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*
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* void foo()
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* {
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* #if QT_COMPILER_SUPPORTS_HERE(XXX)
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* if (qCpuHasFeature(XXX)) {
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* foo_optimized_xxx();
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* return;
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* }
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* #endif
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* foo_plain();
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* }
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*/
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#if defined(__MINGW64_VERSION_MAJOR) || (defined(Q_CC_MSVC) && !defined(Q_OS_WINCE))
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#include <intrin.h>
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#endif
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#define QT_COMPILER_SUPPORTS(x) (QT_COMPILER_SUPPORTS_ ## x - 0)
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#if (defined(Q_CC_INTEL) || defined(Q_CC_MSVC) \
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|| (defined(Q_CC_GNU) && !defined(Q_CC_CLANG) && (__GNUC__-0) * 100 + (__GNUC_MINOR__-0) >= 409)) \
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&& !defined(QT_BOOTSTRAPPED)
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# define QT_COMPILER_SUPPORTS_SIMD_ALWAYS
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# define QT_COMPILER_SUPPORTS_HERE(x) QT_COMPILER_SUPPORTS(x)
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# if defined(Q_CC_GNU) && !defined(Q_CC_INTEL)
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/* GCC requires attributes for a function */
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# define QT_FUNCTION_TARGET(x) __attribute__((__target__(QT_FUNCTION_TARGET_STRING_ ## x)))
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# else
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# define QT_FUNCTION_TARGET(x)
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# endif
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#else
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# define QT_COMPILER_SUPPORTS_HERE(x) defined(__ ## x ## __)
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# define QT_FUNCTION_TARGET(x)
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#endif
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// SSE intrinsics
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#if defined(__SSE2__) || (defined(QT_COMPILER_SUPPORTS_SSE2) && defined(Q_CC_MSVC))
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#define QT_FUNCTION_TARGET_STRING_SSE2 "sse2"
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#if defined(__SSE2__) || (defined(QT_COMPILER_SUPPORTS_SSE2) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS))
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#if defined(QT_LINUXBASE) || defined(Q_OS_ANDROID_NO_SDK)
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/// this is an evil hack - the posix_memalign declaration in LSB
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/// is wrong - see http://bugs.linuxbase.org/show_bug.cgi?id=2431
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@ -95,27 +170,33 @@
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#endif
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// SSE3 intrinsics
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#if defined(__SSE3__) || (defined(QT_COMPILER_SUPPORTS_SSE3) && defined(Q_CC_MSVC))
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#define QT_FUNCTION_TARGET_STRING_SSE3 "sse3"
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#if defined(__SSE3__) || (defined(QT_COMPILER_SUPPORTS_SSE3) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS))
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#include <pmmintrin.h>
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#endif
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// SSSE3 intrinsics
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#if defined(__SSSE3__) || (defined(QT_COMPILER_SUPPORTS_SSSE3) && defined(Q_CC_MSVC))
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#define QT_FUNCTION_TARGET_STRING_SSSE3 "ssse3"
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#if defined(__SSSE3__) || (defined(QT_COMPILER_SUPPORTS_SSSE3) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS))
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#include <tmmintrin.h>
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#endif
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// SSE4.1 intrinsics
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#if defined(__SSE4_1__) || (defined(QT_COMPILER_SUPPORTS_SSE4_1) && defined(Q_CC_MSVC))
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#define QT_FUNCTION_TARGET_STRING_SSE4_1 "sse4.1"
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#if defined(__SSE4_1__) || (defined(QT_COMPILER_SUPPORTS_SSE4_1) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS))
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#include <smmintrin.h>
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#endif
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// SSE4.2 intrinsics
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#if defined(__SSE4_2__) || (defined(QT_COMPILER_SUPPORTS_SSE4_2) && defined(Q_CC_MSVC))
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#define QT_FUNCTION_TARGET_STRING_SSE4_2 "sse4.2"
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#if defined(__SSE4_2__) || (defined(QT_COMPILER_SUPPORTS_SSE4_2) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS))
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#include <nmmintrin.h>
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#endif
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// AVX intrinsics
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#if defined(__AVX__) || (defined(QT_COMPILER_SUPPORTS_AVX) && defined(Q_CC_MSVC))
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#define QT_FUNCTION_TARGET_STRING_AVX "avx"
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#define QT_FUNCTION_TARGET_STRING_AVX2 "avx2"
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#if defined(__AVX__) || (defined(QT_COMPILER_SUPPORTS_AVX) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS))
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// immintrin.h is the ultimate header, we don't need anything else after this
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#include <immintrin.h>
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@ -147,8 +228,10 @@
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#endif
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// NEON intrinsics
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// note: as of GCC 4.9, does not support function targets for ARM
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#if defined __ARM_NEON__
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#include <arm_neon.h>
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#define QT_FUNCTION_TARGET_STRING_ARM_NEON "neon"
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#endif
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@ -169,12 +252,14 @@
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#endif
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#endif
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#undef QT_COMPILER_SUPPORTS_SIMD_ALWAYS
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QT_BEGIN_NAMESPACE
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enum CPUFeatures {
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IWMMXT = 0x1,
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NEON = 0x2,
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NEON = 0x2, ARM_NEON = NEON,
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SSE2 = 0x4,
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SSE3 = 0x8,
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SSSE3 = 0x10,
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@ -3476,21 +3476,21 @@ void Configure::generateConfigfiles()
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tmpStream << endl << "// Compiler sub-arch support" << endl;
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if (dictionary[ "SSE2" ] == "yes")
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tmpStream << "#define QT_COMPILER_SUPPORTS_SSE2" << endl;
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tmpStream << "#define QT_COMPILER_SUPPORTS_SSE2 1" << endl;
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if (dictionary[ "SSE3" ] == "yes")
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tmpStream << "#define QT_COMPILER_SUPPORTS_SSE3" << endl;
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tmpStream << "#define QT_COMPILER_SUPPORTS_SSE3 1" << endl;
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if (dictionary[ "SSSE3" ] == "yes")
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tmpStream << "#define QT_COMPILER_SUPPORTS_SSSE3" << endl;
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tmpStream << "#define QT_COMPILER_SUPPORTS_SSSE3 1" << endl;
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if (dictionary[ "SSE4_1" ] == "yes")
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tmpStream << "#define QT_COMPILER_SUPPORTS_SSE4_1" << endl;
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tmpStream << "#define QT_COMPILER_SUPPORTS_SSE4_1 1" << endl;
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if (dictionary[ "SSE4_2" ] == "yes")
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tmpStream << "#define QT_COMPILER_SUPPORTS_SSE4_2" << endl;
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tmpStream << "#define QT_COMPILER_SUPPORTS_SSE4_2 1" << endl;
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if (dictionary[ "AVX" ] == "yes")
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tmpStream << "#define QT_COMPILER_SUPPORTS_AVX" << endl;
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tmpStream << "#define QT_COMPILER_SUPPORTS_AVX 1" << endl;
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if (dictionary[ "AVX2" ] == "yes")
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tmpStream << "#define QT_COMPILER_SUPPORTS_AVX2" << endl;
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tmpStream << "#define QT_COMPILER_SUPPORTS_AVX2 1" << endl;
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if (dictionary[ "IWMMXT" ] == "yes")
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tmpStream << "#define QT_COMPILER_SUPPORTS_IWMMXT" << endl;
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tmpStream << "#define QT_COMPILER_SUPPORTS_IWMMXT 1" << endl;
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if (dictionary["QREAL"] != "double")
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tmpStream << "#define QT_COORD_TYPE " << dictionary["QREAL"] << endl;
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