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Add the detection of the compiler macros for more AVX512 features

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Change-Id: I1d1f2c3857824b17185bc47398299ea7f92c5568
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
This commit is contained in:
Thiago Macieira 2014-07-30 09:53:01 -07:00
parent 01cce12820
commit 84f5d4b756
1 changed files with 12 additions and 0 deletions
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12
config.tests/arch/arch.cpp
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@ -85,6 +85,14 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
// AVX512 Conflict Detection, Intel Xeon Phi codename "Knights Landing" // AVX512 Conflict Detection, Intel Xeon Phi codename "Knights Landing"
" avx512cd" " avx512cd"
#endif #endif
#ifdef __AVX512DQ__
// AVX512 Double & Quadword, future Intel Xeon processor
" avx512dq"
#endif
#ifdef __AVX512BW__
// AVX512 Byte & Word, future Intel Xeon processor
" avx512bw"
#endif
#ifdef __AVX512ER__ #ifdef __AVX512ER__
// AVX512 Exponentiation & Reciprocal, Intel Xeon Phi codename "Knights Landing" // AVX512 Exponentiation & Reciprocal, Intel Xeon Phi codename "Knights Landing"
" avx512ef" " avx512ef"
@ -93,6 +101,10 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
// AVX512 Prefetch, Intel Xeon Phi codename "Knights Landing" // AVX512 Prefetch, Intel Xeon Phi codename "Knights Landing"
" avx512pf" " avx512pf"
#endif #endif
#ifdef __AVX512VL__
// AVX512 Vector Length, future Intel Xeon processor
" avx512vl"
#endif
#ifdef __BMI__ #ifdef __BMI__
// Bit Manipulation Instructions 1, Intel Core 4th Generation ("Haswell"), AMD "Bulldozer 2" // Bit Manipulation Instructions 1, Intel Core 4th Generation ("Haswell"), AMD "Bulldozer 2"
" bmi" " bmi"