Add RISC-V detection
Change-Id: I0203c88e0944064841c9f6fe9f8a7888d6c421d1 Reviewed-by: Giuseppe D'Angelo <giuseppe.dangelo@kdab.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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@ -67,6 +67,10 @@
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# define ARCH_PROCESSOR "power"
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#elif defined(Q_PROCESSOR_POWER_64)
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# define ARCH_PROCESSOR "power64"
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#elif defined(Q_PROCESSOR_RISCV_32)
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# define ARCH_PROCESSOR "riscv32"
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#elif defined(Q_PROCESSOR_RISCV_64)
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# define ARCH_PROCESSOR "riscv64"
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#elif defined(Q_PROCESSOR_S390_X)
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# define ARCH_PROCESSOR "s390x"
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#elif defined(Q_PROCESSOR_S390)
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@ -1883,6 +1883,42 @@ bool qSharedBuild() noexcept
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\sa QSysInfo::buildCpuArchitecture()
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*/
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/*!
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\macro Q_PROCESSOR_RISCV
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\relates <QtGlobal>
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\since 5.13
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Defined if the application is compiled for RISC-V processors. Qt currently
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supports two RISC-V variants: \l Q_PROCESSOR_RISCV_32 and \l
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Q_PROCESSOR_RISCV_64.
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\sa QSysInfo::buildCpuArchitecture()
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*/
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/*!
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\macro Q_PROCESSOR_RISCV_32
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\relates <QtGlobal>
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\since 5.13
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Defined if the application is compiled for 32-bit RISC-V processors. The \l
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Q_PROCESSOR_RISCV macro is also defined when Q_PROCESSOR_RISCV_32 is
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defined.
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\sa QSysInfo::buildCpuArchitecture()
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*/
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/*!
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\macro Q_PROCESSOR_RISCV_64
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\relates <QtGlobal>
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\since 5.13
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Defined if the application is compiled for 64-bit RISC-V processors. The \l
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Q_PROCESSOR_RISCV macro is also defined when Q_PROCESSOR_RISCV_64 is
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defined.
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\sa QSysInfo::buildCpuArchitecture()
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*/
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/*!
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\macro Q_PROCESSOR_S390
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\relates <QtGlobal>
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@ -281,6 +281,20 @@
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# endif
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// Q_BYTE_ORDER not defined, use endianness auto-detection
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/*
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RISC-V family, known variants: 32- and 64-bit
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RISC-V is little-endian.
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*/
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#elif defined(__riscv)
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# define Q_PROCESSOR_RISCV
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# if __riscv_xlen == 64
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# define Q_PROCESSOR_RISCV_64
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# else
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# define Q_PROCESSOR_RISCV_32
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# endif
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# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
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/*
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S390 family, known variant: S390X (64-bit)
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