Unify the atomic implementation for x86 architectures
It's almost exactly the same code in both files, so let's have one file only. That means we need an #ifdef for the special case of 64-bit types on i386. Also take the opportunity to add a comment explaining how this works. Change-Id: I50d274fa026806ae511b1045aa8a5c25daaa0edc Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
This commit is contained in:
Thiago Macieira
Qt by Nokia
parent
4408d0ccd8
commit
e7a6dacf80
@ -9,7 +9,6 @@ HEADERS += \
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arch/qatomic_armv7.h \
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arch/qatomic_armv7.h \
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arch/qatomic_bfin.h \
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arch/qatomic_bfin.h \
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arch/qatomic_bootstrap.h \
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arch/qatomic_bootstrap.h \
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arch/qatomic_i386.h \
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arch/qatomic_ia64.h \
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arch/qatomic_ia64.h \
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arch/qatomic_mips.h \
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arch/qatomic_mips.h \
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arch/qatomic_power.h \
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arch/qatomic_power.h \
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@ -1,358 +0,0 @@
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/****************************************************************************
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**
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** Copyright (C) 2012 Nokia Corporation and/or its subsidiary(-ies).
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** Copyright (C) 2011 Thiago Macieira <thiago@kde.org>
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** Contact: http://www.qt-project.org/
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**
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** This file is part of the QtCore module of the Qt Toolkit.
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**
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** $QT_BEGIN_LICENSE:LGPL$
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** GNU Lesser General Public License Usage
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** This file may be used under the terms of the GNU Lesser General Public
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** License version 2.1 as published by the Free Software Foundation and
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** appearing in the file LICENSE.LGPL included in the packaging of this
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** file. Please review the following information to ensure the GNU Lesser
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** General Public License version 2.1 requirements will be met:
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** http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html.
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**
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** In addition, as a special exception, Nokia gives you certain additional
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** rights. These rights are described in the Nokia Qt LGPL Exception
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** version 1.1, included in the file LGPL_EXCEPTION.txt in this package.
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**
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** GNU General Public License Usage
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** Alternatively, this file may be used under the terms of the GNU General
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** Public License version 3.0 as published by the Free Software Foundation
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** and appearing in the file LICENSE.GPL included in the packaging of this
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** file. Please review the following information to ensure the GNU General
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** Public License version 3.0 requirements will be met:
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** http://www.gnu.org/copyleft/gpl.html.
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**
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** Other Usage
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** Alternatively, this file may be used in accordance with the terms and
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** conditions contained in a signed written agreement between you and Nokia.
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**
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**
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**
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**
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**
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**
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** $QT_END_LICENSE$
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**
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****************************************************************************/
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#ifndef QATOMIC_I386_H
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#define QATOMIC_I386_H
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#include <QtCore/qgenericatomic.h>
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QT_BEGIN_HEADER
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QT_BEGIN_NAMESPACE
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#if 0
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// silence syncqt warnings
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QT_END_NAMESPACE
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QT_END_HEADER
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#pragma qt_sync_stop_processing
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#endif
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template<> struct QAtomicIntegerTraits<int> { enum { IsInteger = 1 }; };
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template<> struct QAtomicIntegerTraits<unsigned int> { enum { IsInteger = 1 }; };
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#define Q_ATOMIC_INT_REFERENCE_COUNTING_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT_REFERENCE_COUNTING_IS_WAIT_FREE
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#define Q_ATOMIC_INT_TEST_AND_SET_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT_TEST_AND_SET_IS_WAIT_FREE
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#define Q_ATOMIC_INT_FETCH_AND_STORE_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT_FETCH_AND_STORE_IS_WAIT_FREE
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#define Q_ATOMIC_INT_FETCH_AND_ADD_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT_FETCH_AND_ADD_IS_WAIT_FREE
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#define Q_ATOMIC_INT32_IS_SUPPORTED
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#define Q_ATOMIC_INT32_REFERENCE_COUNTING_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT32_REFERENCE_COUNTING_IS_WAIT_FREE
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#define Q_ATOMIC_INT32_TEST_AND_SET_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT32_TEST_AND_SET_IS_WAIT_FREE
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#define Q_ATOMIC_INT32_FETCH_AND_STORE_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT32_FETCH_AND_STORE_IS_WAIT_FREE
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#define Q_ATOMIC_INT32_FETCH_AND_ADD_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT32_FETCH_AND_ADD_IS_WAIT_FREE
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#define Q_ATOMIC_POINTER_TEST_AND_SET_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_POINTER_TEST_AND_SET_IS_WAIT_FREE
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#define Q_ATOMIC_POINTER_FETCH_AND_STORE_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_POINTER_FETCH_AND_STORE_IS_WAIT_FREE
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#define Q_ATOMIC_POINTER_FETCH_AND_ADD_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_POINTER_FETCH_AND_ADD_IS_WAIT_FREE
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template <int size> struct QBasicAtomicOps: QGenericAtomicOps<QBasicAtomicOps<size> >
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{
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static inline bool isReferenceCountingNative() { return true; }
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static inline bool isReferenceCountingWaitFree() { return true; }
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template <typename T> static bool ref(T &_q_value);
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template <typename T> static bool deref(T &_q_value);
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static inline bool isTestAndSetNative() { return true; }
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static inline bool isTestAndSetWaitFree() { return true; }
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template <typename T> static bool testAndSetRelaxed(T &_q_value, T expectedValue, T newValue);
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static inline bool isFetchAndStoreNative() { return true; }
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static inline bool isFetchAndStoreWaitFree() { return true; }
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template <typename T> static T fetchAndStoreRelaxed(T &_q_value, T newValue);
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static inline bool isFetchAndAddNative() { return true; }
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static inline bool isFetchAndAddWaitFree() { return true; }
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template <typename T> static
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T fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveType<T>::AdditiveT valueToAdd);
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};
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template <typename T> struct QAtomicOps : QBasicAtomicOps<sizeof(T)>
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{
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typedef T Type;
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};
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#if defined(Q_CC_GNU) || defined(Q_CC_INTEL)
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template<> struct QAtomicIntegerTraits<char> { enum { IsInteger = 1 }; };
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template<> struct QAtomicIntegerTraits<signed char> { enum { IsInteger = 1 }; };
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template<> struct QAtomicIntegerTraits<unsigned char> { enum { IsInteger = 1 }; };
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template<> struct QAtomicIntegerTraits<short> { enum { IsInteger = 1 }; };
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template<> struct QAtomicIntegerTraits<unsigned short> { enum { IsInteger = 1 }; };
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template<> struct QAtomicIntegerTraits<long> { enum { IsInteger = 1 }; };
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template<> struct QAtomicIntegerTraits<unsigned long> { enum { IsInteger = 1 }; };
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template<> struct QAtomicIntegerTraits<long long> { enum { IsInteger = 1 }; };
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template<> struct QAtomicIntegerTraits<unsigned long long> { enum { IsInteger = 1 }; };
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template<> template<typename T> inline
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bool QBasicAtomicOps<1>::ref(T &_q_value)
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{
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unsigned char ret;
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asm volatile("lock\n"
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"addb $1, %0\n"
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"setne %1"
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: "+m" (_q_value), "=qm" (ret)
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:
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: "memory");
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return ret != 0;
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}
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template<> template<typename T> inline
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bool QBasicAtomicOps<2>::ref(T &_q_value)
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{
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unsigned char ret;
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asm volatile("lock\n"
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"incw %0\n"
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"setne %1"
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: "+m" (_q_value), "=qm" (ret)
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:
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: "memory");
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return ret != 0;
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}
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template<> template<typename T> inline
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bool QBasicAtomicOps<4>::ref(T &_q_value)
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{
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unsigned char ret;
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asm volatile("lock\n"
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"addl $1, %0\n"
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"setne %1"
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: "+m" (_q_value), "=qm" (ret)
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:
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: "memory");
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return ret != 0;
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}
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template<> template <typename T> inline
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bool QBasicAtomicOps<1>::deref(T &_q_value)
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{
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unsigned char ret;
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asm volatile("lock\n"
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"subb $1, %0\n"
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"setne %1"
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: "+m" (_q_value), "=qm" (ret)
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:
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: "memory");
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return ret != 0;
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}
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template<> template <typename T> inline
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bool QBasicAtomicOps<2>::deref(T &_q_value)
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{
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unsigned char ret;
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asm volatile("lock\n"
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"decw %0\n"
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"setne %1"
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: "+m" (_q_value), "=qm" (ret)
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:
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: "memory");
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return ret != 0;
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}
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template<> template <typename T> inline
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bool QBasicAtomicOps<4>::deref(T &_q_value)
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{
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unsigned char ret;
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asm volatile("lock\n"
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"subl $1, %0\n"
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"setne %1"
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: "+m" (_q_value), "=qm" (ret)
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:
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: "memory");
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return ret != 0;
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}
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template<int size> template <typename T> inline
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bool QBasicAtomicOps<size>::testAndSetRelaxed(T &_q_value, T expectedValue, T newValue)
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{
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unsigned char ret;
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asm volatile("lock\n"
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"cmpxchg %3,%2\n"
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"sete %1\n"
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: "=a" (newValue), "=qm" (ret), "+m" (_q_value)
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: "r" (newValue), "0" (expectedValue)
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: "memory");
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return ret != 0;
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}
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template<> template <typename T> inline
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bool QBasicAtomicOps<1>::testAndSetRelaxed(T &_q_value, T expectedValue, T newValue)
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{
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unsigned char ret;
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asm volatile("lock\n"
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"cmpxchg %3,%2\n"
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"sete %1\n"
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: "=a" (newValue), "=qm" (ret), "+m" (_q_value)
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: "q" (newValue), "0" (expectedValue)
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: "memory");
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return ret != 0;
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}
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template<int size> template <typename T> inline
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T QBasicAtomicOps<size>::fetchAndStoreRelaxed(T &_q_value, T newValue)
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{
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asm volatile("xchg %0,%1"
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: "=r" (newValue), "+m" (_q_value)
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: "0" (newValue)
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: "memory");
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return newValue;
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}
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template<> template <typename T> inline
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T QBasicAtomicOps<1>::fetchAndStoreRelaxed(T &_q_value, T newValue)
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{
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asm volatile("xchg %0,%1"
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: "=q" (newValue), "+m" (_q_value)
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: "0" (newValue)
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: "memory");
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return newValue;
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}
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template<int size> template <typename T> inline
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T QBasicAtomicOps<size>::fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveType<T>::AdditiveT valueToAdd)
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{
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T result;
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asm volatile("lock\n"
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"xadd %0,%1"
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: "=r" (result), "+m" (_q_value)
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: "0" (T(valueToAdd * QAtomicAdditiveType<T>::AddScale))
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: "memory");
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return result;
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}
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template<> template <typename T> inline
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T QBasicAtomicOps<1>::fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveType<T>::AdditiveT valueToAdd)
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{
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T result;
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asm volatile("lock\n"
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"xadd %0,%1"
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: "=q" (result), "+m" (_q_value)
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: "0" (T(valueToAdd * QAtomicAdditiveType<T>::AddScale))
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: "memory");
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return result;
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}
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#define Q_ATOMIC_INT8_IS_SUPPORTED
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#define Q_ATOMIC_INT8_REFERENCE_COUNTING_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT8_REFERENCE_COUNTING_IS_WAIT_FREE
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#define Q_ATOMIC_INT8_TEST_AND_SET_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT8_TEST_AND_SET_IS_WAIT_FREE
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#define Q_ATOMIC_INT8_FETCH_AND_STORE_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT8_FETCH_AND_STORE_IS_WAIT_FREE
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#define Q_ATOMIC_INT8_FETCH_AND_ADD_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT8_FETCH_AND_ADD_IS_WAIT_FREE
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#define Q_ATOMIC_INT16_IS_SUPPORTED
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#define Q_ATOMIC_INT16_REFERENCE_COUNTING_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT16_REFERENCE_COUNTING_IS_WAIT_FREE
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#define Q_ATOMIC_INT16_TEST_AND_SET_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT16_TEST_AND_SET_IS_WAIT_FREE
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#define Q_ATOMIC_INT16_FETCH_AND_STORE_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT16_FETCH_AND_STORE_IS_WAIT_FREE
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#define Q_ATOMIC_INT16_FETCH_AND_ADD_IS_ALWAYS_NATIVE
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#define Q_ATOMIC_INT16_FETCH_AND_ADD_IS_WAIT_FREE
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template <> struct QBasicAtomicOps<8>: QGenericAtomicOps<QBasicAtomicOps<8> >
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{
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static inline bool isTestAndSetNative() { return true; }
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static inline bool isTestAndSetWaitFree() { return true; }
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template <typename T> static inline
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bool testAndSetRelaxed(T &_q_value, T expectedValue, T newValue)
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{
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#ifdef __PIC__
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# define EBX_reg "r"
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# define EBX_load(reg) "xchg " reg ", %%ebx\n"
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#else
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# define EBX_reg "b"
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# define EBX_load(reg)
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#endif
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quint32 highExpectedValue = quint32(newValue >> 32); // ECX
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asm volatile(EBX_load("%3")
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"lock\n"
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"cmpxchg8b %0\n"
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EBX_load("%3")
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"sete %%cl\n"
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: "+m" (_q_value), "+c" (highExpectedValue), "+&A" (expectedValue)
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: EBX_reg (quint32(newValue & 0xffffffff))
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: "memory");
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// if the comparison failed, expectedValue here contains the current value
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return quint8(highExpectedValue) != 0;
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#undef EBX_reg
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#undef EBX_load
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}
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};
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#define Q_ATOMIC_INT64_IS_SUPPORTED
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|
||||||
#define Q_ATOMIC_INT64_REFERENCE_COUNTING_IS_NOT_NATIVE
|
|
||||||
|
|
||||||
#define Q_ATOMIC_INT64_TEST_AND_SET_IS_NOT_NATIVE
|
|
||||||
#define Q_ATOMIC_INT64_TEST_AND_SET_IS_WAIT_FREE
|
|
||||||
|
|
||||||
#define Q_ATOMIC_INT64_FETCH_AND_STORE_IS_NATIVE
|
|
||||||
|
|
||||||
#define Q_ATOMIC_INT64_FETCH_AND_ADD_IS_NOT_NATIVE
|
|
||||||
|
|
||||||
#else
|
|
||||||
# error "This compiler for i386 is not supported"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
QT_END_NAMESPACE
|
|
||||||
QT_END_HEADER
|
|
||||||
|
|
||||||
#endif // QATOMIC_I386_H
|
|
||||||
@ -40,8 +40,8 @@
|
|||||||
**
|
**
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
#ifndef QATOMIC_X86_64_H
|
#ifndef QATOMIC_X86_H
|
||||||
#define QATOMIC_X86_64_H
|
#define QATOMIC_X86_H
|
||||||
|
|
||||||
#include <QtCore/qgenericatomic.h>
|
#include <QtCore/qgenericatomic.h>
|
||||||
|
|
||||||
@ -121,7 +121,7 @@ template <typename T> struct QAtomicOps : QBasicAtomicOps<sizeof(T)>
|
|||||||
typedef T Type;
|
typedef T Type;
|
||||||
};
|
};
|
||||||
|
|
||||||
#if defined(Q_CC_GNU) || defined(Q_CC_INTEL)
|
#if defined(Q_CC_GNU)
|
||||||
|
|
||||||
template<> struct QAtomicIntegerTraits<char> { enum { IsInteger = 1 }; };
|
template<> struct QAtomicIntegerTraits<char> { enum { IsInteger = 1 }; };
|
||||||
template<> struct QAtomicIntegerTraits<signed char> { enum { IsInteger = 1 }; };
|
template<> struct QAtomicIntegerTraits<signed char> { enum { IsInteger = 1 }; };
|
||||||
@ -133,6 +133,34 @@ template<> struct QAtomicIntegerTraits<unsigned long> { enum { IsInteger = 1 };
|
|||||||
template<> struct QAtomicIntegerTraits<long long> { enum { IsInteger = 1 }; };
|
template<> struct QAtomicIntegerTraits<long long> { enum { IsInteger = 1 }; };
|
||||||
template<> struct QAtomicIntegerTraits<unsigned long long> { enum { IsInteger = 1 }; };
|
template<> struct QAtomicIntegerTraits<unsigned long long> { enum { IsInteger = 1 }; };
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Guide for the inline assembly below:
|
||||||
|
*
|
||||||
|
* x86 instructions are in the form "{opcode}{length} {source}, {destination}",
|
||||||
|
* where the length is one of the letters "b" (byte), "w" (word, 16-bit), "l"
|
||||||
|
* (dword, 32-bit), "q" (qword, 64-bit).
|
||||||
|
*
|
||||||
|
* In most cases, we can omit the length because it's inferred from one of the
|
||||||
|
* registers. For example, "xchg %0,%1" doesn't need the length suffix because
|
||||||
|
* we can only exchange data of the same size and one of the operands must be a
|
||||||
|
* register.
|
||||||
|
*
|
||||||
|
* The exception is the increment and decrement functions, where we add and
|
||||||
|
* subtract an immediate value (1). For those, we need to specify the length.
|
||||||
|
* GCC and ICC support the syntax "add%z0 $1, %0", where "%z0" expands to the
|
||||||
|
* length of the operand. Unfortunately, clang as of 3.0 doesn't support that.
|
||||||
|
* For that reason, the ref() and deref() functions are rolled out for all
|
||||||
|
* sizes.
|
||||||
|
*
|
||||||
|
* The functions are also rolled out for the 1-byte operations since those
|
||||||
|
* require a special register constraint "q" to force the compiler to schedule
|
||||||
|
* one of the 8-bit registers. It's probably a compiler bug that it tries to
|
||||||
|
* use a register that doesn't exist.
|
||||||
|
*
|
||||||
|
* Finally, 64-bit operations are supported via the cmpxchg8b instruction on
|
||||||
|
* 32-bit processors, via specialisation below.
|
||||||
|
*/
|
||||||
|
|
||||||
template<> template<typename T> inline
|
template<> template<typename T> inline
|
||||||
bool QBasicAtomicOps<1>::ref(T &_q_value)
|
bool QBasicAtomicOps<1>::ref(T &_q_value)
|
||||||
{
|
{
|
||||||
@ -172,19 +200,6 @@ bool QBasicAtomicOps<4>::ref(T &_q_value)
|
|||||||
return ret != 0;
|
return ret != 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
template<> template<typename T> inline
|
|
||||||
bool QBasicAtomicOps<8>::ref(T &_q_value)
|
|
||||||
{
|
|
||||||
unsigned char ret;
|
|
||||||
asm volatile("lock\n"
|
|
||||||
"addq $1, %0\n"
|
|
||||||
"setne %1"
|
|
||||||
: "=m" (_q_value), "=qm" (ret)
|
|
||||||
: "m" (_q_value)
|
|
||||||
: "memory");
|
|
||||||
return ret != 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
template<> template <typename T> inline
|
template<> template <typename T> inline
|
||||||
bool QBasicAtomicOps<1>::deref(T &_q_value)
|
bool QBasicAtomicOps<1>::deref(T &_q_value)
|
||||||
{
|
{
|
||||||
@ -223,19 +238,6 @@ bool QBasicAtomicOps<4>::deref(T &_q_value)
|
|||||||
return ret != 0;
|
return ret != 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
template<> template <typename T> inline
|
|
||||||
bool QBasicAtomicOps<8>::deref(T &_q_value)
|
|
||||||
{
|
|
||||||
unsigned char ret;
|
|
||||||
asm volatile("lock\n"
|
|
||||||
"subq $1, %0\n"
|
|
||||||
"setne %1"
|
|
||||||
: "=m" (_q_value), "=qm" (ret)
|
|
||||||
: "m" (_q_value)
|
|
||||||
: "memory");
|
|
||||||
return ret != 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
template<int size> template <typename T> inline
|
template<int size> template <typename T> inline
|
||||||
bool QBasicAtomicOps<size>::testAndSetRelaxed(T &_q_value, T expectedValue, T newValue)
|
bool QBasicAtomicOps<size>::testAndSetRelaxed(T &_q_value, T expectedValue, T newValue)
|
||||||
{
|
{
|
||||||
@ -348,12 +350,73 @@ T QBasicAtomicOps<1>::fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveTy
|
|||||||
#define Q_ATOMIC_INT64_FETCH_AND_ADD_IS_ALWAYS_NATIVE
|
#define Q_ATOMIC_INT64_FETCH_AND_ADD_IS_ALWAYS_NATIVE
|
||||||
#define Q_ATOMIC_INT64_FETCH_AND_ADD_IS_WAIT_FREE
|
#define Q_ATOMIC_INT64_FETCH_AND_ADD_IS_WAIT_FREE
|
||||||
|
|
||||||
#else // !Q_CC_INTEL && !Q_CC_GNU
|
#ifdef Q_PROCESSOR_X86_64
|
||||||
# error "This compiler for x86_64 is not supported"
|
// native support for 64-bit types
|
||||||
#endif // Q_CC_GNU || Q_CC_INTEL
|
template<> template<typename T> inline
|
||||||
|
bool QBasicAtomicOps<8>::ref(T &_q_value)
|
||||||
|
{
|
||||||
|
unsigned char ret;
|
||||||
|
asm volatile("lock\n"
|
||||||
|
"addq $1, %0\n"
|
||||||
|
"setne %1"
|
||||||
|
: "=m" (_q_value), "=qm" (ret)
|
||||||
|
: "m" (_q_value)
|
||||||
|
: "memory");
|
||||||
|
return ret != 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<> template <typename T> inline
|
||||||
|
bool QBasicAtomicOps<8>::deref(T &_q_value)
|
||||||
|
{
|
||||||
|
unsigned char ret;
|
||||||
|
asm volatile("lock\n"
|
||||||
|
"subq $1, %0\n"
|
||||||
|
"setne %1"
|
||||||
|
: "=m" (_q_value), "=qm" (ret)
|
||||||
|
: "m" (_q_value)
|
||||||
|
: "memory");
|
||||||
|
return ret != 0;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
// i386 architecture, emulate 64-bit support via cmpxchg8b
|
||||||
|
template <> struct QBasicAtomicOps<8>: QGenericAtomicOps<QBasicAtomicOps<8> >
|
||||||
|
{
|
||||||
|
static inline bool isTestAndSetNative() { return true; }
|
||||||
|
static inline bool isTestAndSetWaitFree() { return true; }
|
||||||
|
template <typename T> static inline
|
||||||
|
bool testAndSetRelaxed(T &_q_value, T expectedValue, T newValue)
|
||||||
|
{
|
||||||
|
#ifdef __PIC__
|
||||||
|
# define EBX_reg "r"
|
||||||
|
# define EBX_load(reg) "xchg " reg ", %%ebx\n"
|
||||||
|
#else
|
||||||
|
# define EBX_reg "b"
|
||||||
|
# define EBX_load(reg)
|
||||||
|
#endif
|
||||||
|
quint32 highExpectedValue = quint32(newValue >> 32); // ECX
|
||||||
|
asm volatile(EBX_load("%3")
|
||||||
|
"lock\n"
|
||||||
|
"cmpxchg8b %0\n"
|
||||||
|
EBX_load("%3")
|
||||||
|
"sete %%cl\n"
|
||||||
|
: "+m" (_q_value), "+c" (highExpectedValue), "+&A" (expectedValue)
|
||||||
|
: EBX_reg (quint32(newValue & 0xffffffff))
|
||||||
|
: "memory");
|
||||||
|
// if the comparison failed, expectedValue here contains the current value
|
||||||
|
return quint8(highExpectedValue) != 0;
|
||||||
|
#undef EBX_reg
|
||||||
|
#undef EBX_load
|
||||||
|
}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else
|
||||||
|
# error "This compiler for x86 is not supported"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
QT_END_NAMESPACE
|
QT_END_NAMESPACE
|
||||||
|
|
||||||
QT_END_HEADER
|
QT_END_HEADER
|
||||||
|
|
||||||
#endif // QATOMIC_X86_64_H
|
#endif // QATOMIC_X86_H
|
||||||
|
|||||||
@ -80,8 +80,6 @@
|
|||||||
# include "QtCore/qatomic_sh4a.h"
|
# include "QtCore/qatomic_sh4a.h"
|
||||||
#elif defined(Q_PROCESSOR_SPARC)
|
#elif defined(Q_PROCESSOR_SPARC)
|
||||||
# include "QtCore/qatomic_sparc.h"
|
# include "QtCore/qatomic_sparc.h"
|
||||||
#elif defined(Q_PROCESSOR_X86_32)
|
|
||||||
# include <QtCore/qatomic_i386.h>
|
|
||||||
#elif defined(Q_PROCESSOR_X86)
|
#elif defined(Q_PROCESSOR_X86)
|
||||||
# include <QtCore/qatomic_x86.h>
|
# include <QtCore/qatomic_x86.h>
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user