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Unify the atomic implementation for x86 architectures

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It's almost exactly the same code in both files, so let's have one file
only. That means we need an #ifdef for the special case of 64-bit types
on i386.

Also take the opportunity to add a comment explaining how this works.

Change-Id: I50d274fa026806ae511b1045aa8a5c25daaa0edc
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
This commit is contained in:
Thiago Macieira 2012-02-27 16:01:53 +01:00 committed by Qt by Nokia
parent 4408d0ccd8
commit e7a6dacf80
4 changed files with 96 additions and 394 deletions
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1
src/corelib/arch/arch.pri
View File

@ -9,7 +9,6 @@ HEADERS += \
arch/qatomic_armv7.h \
arch/qatomic_bfin.h \
arch/qatomic_bootstrap.h \
arch/qatomic_i386.h \
arch/qatomic_ia64.h \
arch/qatomic_mips.h \
arch/qatomic_power.h \

358
src/corelib/arch/qatomic_i386.h
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@ -1,358 +0,0 @@
/****************************************************************************
**
** Copyright (C) 2012 Nokia Corporation and/or its subsidiary(-ies).
** Copyright (C) 2011 Thiago Macieira <thiago@kde.org>
** Contact: http://www.qt-project.org/
**
** This file is part of the QtCore module of the Qt Toolkit.
**
** $QT_BEGIN_LICENSE:LGPL$
** GNU Lesser General Public License Usage
** This file may be used under the terms of the GNU Lesser General Public
** License version 2.1 as published by the Free Software Foundation and
** appearing in the file LICENSE.LGPL included in the packaging of this
** file. Please review the following information to ensure the GNU Lesser
** General Public License version 2.1 requirements will be met:
** http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html.
**
** In addition, as a special exception, Nokia gives you certain additional
** rights. These rights are described in the Nokia Qt LGPL Exception
** version 1.1, included in the file LGPL_EXCEPTION.txt in this package.
**
** GNU General Public License Usage
** Alternatively, this file may be used under the terms of the GNU General
** Public License version 3.0 as published by the Free Software Foundation
** and appearing in the file LICENSE.GPL included in the packaging of this
** file. Please review the following information to ensure the GNU General
** Public License version 3.0 requirements will be met:
** http://www.gnu.org/copyleft/gpl.html.
**
** Other Usage
** Alternatively, this file may be used in accordance with the terms and
** conditions contained in a signed written agreement between you and Nokia.
**
**
**
**
**
**
** $QT_END_LICENSE$
**
****************************************************************************/
#ifndef QATOMIC_I386_H
#define QATOMIC_I386_H
#include <QtCore/qgenericatomic.h>
QT_BEGIN_HEADER
QT_BEGIN_NAMESPACE
#if 0
// silence syncqt warnings
QT_END_NAMESPACE
QT_END_HEADER
#pragma qt_sync_stop_processing
#endif
template<> struct QAtomicIntegerTraits<int> { enum { IsInteger = 1 }; };
template<> struct QAtomicIntegerTraits<unsigned int> { enum { IsInteger = 1 }; };
#define Q_ATOMIC_INT_REFERENCE_COUNTING_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT_REFERENCE_COUNTING_IS_WAIT_FREE
#define Q_ATOMIC_INT_TEST_AND_SET_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT_TEST_AND_SET_IS_WAIT_FREE
#define Q_ATOMIC_INT_FETCH_AND_STORE_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT_FETCH_AND_STORE_IS_WAIT_FREE
#define Q_ATOMIC_INT_FETCH_AND_ADD_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT_FETCH_AND_ADD_IS_WAIT_FREE
#define Q_ATOMIC_INT32_IS_SUPPORTED
#define Q_ATOMIC_INT32_REFERENCE_COUNTING_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT32_REFERENCE_COUNTING_IS_WAIT_FREE
#define Q_ATOMIC_INT32_TEST_AND_SET_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT32_TEST_AND_SET_IS_WAIT_FREE
#define Q_ATOMIC_INT32_FETCH_AND_STORE_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT32_FETCH_AND_STORE_IS_WAIT_FREE
#define Q_ATOMIC_INT32_FETCH_AND_ADD_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT32_FETCH_AND_ADD_IS_WAIT_FREE
#define Q_ATOMIC_POINTER_TEST_AND_SET_IS_ALWAYS_NATIVE
#define Q_ATOMIC_POINTER_TEST_AND_SET_IS_WAIT_FREE
#define Q_ATOMIC_POINTER_FETCH_AND_STORE_IS_ALWAYS_NATIVE
#define Q_ATOMIC_POINTER_FETCH_AND_STORE_IS_WAIT_FREE
#define Q_ATOMIC_POINTER_FETCH_AND_ADD_IS_ALWAYS_NATIVE
#define Q_ATOMIC_POINTER_FETCH_AND_ADD_IS_WAIT_FREE
template <int size> struct QBasicAtomicOps: QGenericAtomicOps<QBasicAtomicOps<size> >
{
static inline bool isReferenceCountingNative() { return true; }
static inline bool isReferenceCountingWaitFree() { return true; }
template <typename T> static bool ref(T &_q_value);
template <typename T> static bool deref(T &_q_value);
static inline bool isTestAndSetNative() { return true; }
static inline bool isTestAndSetWaitFree() { return true; }
template <typename T> static bool testAndSetRelaxed(T &_q_value, T expectedValue, T newValue);
static inline bool isFetchAndStoreNative() { return true; }
static inline bool isFetchAndStoreWaitFree() { return true; }
template <typename T> static T fetchAndStoreRelaxed(T &_q_value, T newValue);
static inline bool isFetchAndAddNative() { return true; }
static inline bool isFetchAndAddWaitFree() { return true; }
template <typename T> static
T fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveType<T>::AdditiveT valueToAdd);
};
template <typename T> struct QAtomicOps : QBasicAtomicOps<sizeof(T)>
{
typedef T Type;
};
#if defined(Q_CC_GNU) || defined(Q_CC_INTEL)
template<> struct QAtomicIntegerTraits<char> { enum { IsInteger = 1 }; };
template<> struct QAtomicIntegerTraits<signed char> { enum { IsInteger = 1 }; };
template<> struct QAtomicIntegerTraits<unsigned char> { enum { IsInteger = 1 }; };
template<> struct QAtomicIntegerTraits<short> { enum { IsInteger = 1 }; };
template<> struct QAtomicIntegerTraits<unsigned short> { enum { IsInteger = 1 }; };
template<> struct QAtomicIntegerTraits<long> { enum { IsInteger = 1 }; };
template<> struct QAtomicIntegerTraits<unsigned long> { enum { IsInteger = 1 }; };
template<> struct QAtomicIntegerTraits<long long> { enum { IsInteger = 1 }; };
template<> struct QAtomicIntegerTraits<unsigned long long> { enum { IsInteger = 1 }; };
template<> template<typename T> inline
bool QBasicAtomicOps<1>::ref(T &_q_value)
{
unsigned char ret;
asm volatile("lock\n"
"addb $1, %0\n"
"setne %1"
: "+m" (_q_value), "=qm" (ret)
:
: "memory");
return ret != 0;
}
template<> template<typename T> inline
bool QBasicAtomicOps<2>::ref(T &_q_value)
{
unsigned char ret;
asm volatile("lock\n"
"incw %0\n"
"setne %1"
: "+m" (_q_value), "=qm" (ret)
:
: "memory");
return ret != 0;
}
template<> template<typename T> inline
bool QBasicAtomicOps<4>::ref(T &_q_value)
{
unsigned char ret;
asm volatile("lock\n"
"addl $1, %0\n"
"setne %1"
: "+m" (_q_value), "=qm" (ret)
:
: "memory");
return ret != 0;
}
template<> template <typename T> inline
bool QBasicAtomicOps<1>::deref(T &_q_value)
{
unsigned char ret;
asm volatile("lock\n"
"subb $1, %0\n"
"setne %1"
: "+m" (_q_value), "=qm" (ret)
:
: "memory");
return ret != 0;
}
template<> template <typename T> inline
bool QBasicAtomicOps<2>::deref(T &_q_value)
{
unsigned char ret;
asm volatile("lock\n"
"decw %0\n"
"setne %1"
: "+m" (_q_value), "=qm" (ret)
:
: "memory");
return ret != 0;
}
template<> template <typename T> inline
bool QBasicAtomicOps<4>::deref(T &_q_value)
{
unsigned char ret;
asm volatile("lock\n"
"subl $1, %0\n"
"setne %1"
: "+m" (_q_value), "=qm" (ret)
:
: "memory");
return ret != 0;
}
template<int size> template <typename T> inline
bool QBasicAtomicOps<size>::testAndSetRelaxed(T &_q_value, T expectedValue, T newValue)
{
unsigned char ret;
asm volatile("lock\n"
"cmpxchg %3,%2\n"
"sete %1\n"
: "=a" (newValue), "=qm" (ret), "+m" (_q_value)
: "r" (newValue), "0" (expectedValue)
: "memory");
return ret != 0;
}
template<> template <typename T> inline
bool QBasicAtomicOps<1>::testAndSetRelaxed(T &_q_value, T expectedValue, T newValue)
{
unsigned char ret;
asm volatile("lock\n"
"cmpxchg %3,%2\n"
"sete %1\n"
: "=a" (newValue), "=qm" (ret), "+m" (_q_value)
: "q" (newValue), "0" (expectedValue)
: "memory");
return ret != 0;
}
template<int size> template <typename T> inline
T QBasicAtomicOps<size>::fetchAndStoreRelaxed(T &_q_value, T newValue)
{
asm volatile("xchg %0,%1"
: "=r" (newValue), "+m" (_q_value)
: "0" (newValue)
: "memory");
return newValue;
}
template<> template <typename T> inline
T QBasicAtomicOps<1>::fetchAndStoreRelaxed(T &_q_value, T newValue)
{
asm volatile("xchg %0,%1"
: "=q" (newValue), "+m" (_q_value)
: "0" (newValue)
: "memory");
return newValue;
}
template<int size> template <typename T> inline
T QBasicAtomicOps<size>::fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveType<T>::AdditiveT valueToAdd)
{
T result;
asm volatile("lock\n"
"xadd %0,%1"
: "=r" (result), "+m" (_q_value)
: "0" (T(valueToAdd * QAtomicAdditiveType<T>::AddScale))
: "memory");
return result;
}
template<> template <typename T> inline
T QBasicAtomicOps<1>::fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveType<T>::AdditiveT valueToAdd)
{
T result;
asm volatile("lock\n"
"xadd %0,%1"
: "=q" (result), "+m" (_q_value)
: "0" (T(valueToAdd * QAtomicAdditiveType<T>::AddScale))
: "memory");
return result;
}
#define Q_ATOMIC_INT8_IS_SUPPORTED
#define Q_ATOMIC_INT8_REFERENCE_COUNTING_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT8_REFERENCE_COUNTING_IS_WAIT_FREE
#define Q_ATOMIC_INT8_TEST_AND_SET_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT8_TEST_AND_SET_IS_WAIT_FREE
#define Q_ATOMIC_INT8_FETCH_AND_STORE_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT8_FETCH_AND_STORE_IS_WAIT_FREE
#define Q_ATOMIC_INT8_FETCH_AND_ADD_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT8_FETCH_AND_ADD_IS_WAIT_FREE
#define Q_ATOMIC_INT16_IS_SUPPORTED
#define Q_ATOMIC_INT16_REFERENCE_COUNTING_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT16_REFERENCE_COUNTING_IS_WAIT_FREE
#define Q_ATOMIC_INT16_TEST_AND_SET_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT16_TEST_AND_SET_IS_WAIT_FREE
#define Q_ATOMIC_INT16_FETCH_AND_STORE_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT16_FETCH_AND_STORE_IS_WAIT_FREE
#define Q_ATOMIC_INT16_FETCH_AND_ADD_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT16_FETCH_AND_ADD_IS_WAIT_FREE
template <> struct QBasicAtomicOps<8>: QGenericAtomicOps<QBasicAtomicOps<8> >
{
static inline bool isTestAndSetNative() { return true; }
static inline bool isTestAndSetWaitFree() { return true; }
template <typename T> static inline
bool testAndSetRelaxed(T &_q_value, T expectedValue, T newValue)
{
#ifdef __PIC__
# define EBX_reg "r"
# define EBX_load(reg) "xchg " reg ", %%ebx\n"
#else
# define EBX_reg "b"
# define EBX_load(reg)
#endif
quint32 highExpectedValue = quint32(newValue >> 32); // ECX
asm volatile(EBX_load("%3")
"lock\n"
"cmpxchg8b %0\n"
EBX_load("%3")
"sete %%cl\n"
: "+m" (_q_value), "+c" (highExpectedValue), "+&A" (expectedValue)
: EBX_reg (quint32(newValue & 0xffffffff))
: "memory");
// if the comparison failed, expectedValue here contains the current value
return quint8(highExpectedValue) != 0;
#undef EBX_reg
#undef EBX_load
}
};
#define Q_ATOMIC_INT64_IS_SUPPORTED
#define Q_ATOMIC_INT64_REFERENCE_COUNTING_IS_NOT_NATIVE
#define Q_ATOMIC_INT64_TEST_AND_SET_IS_NOT_NATIVE
#define Q_ATOMIC_INT64_TEST_AND_SET_IS_WAIT_FREE
#define Q_ATOMIC_INT64_FETCH_AND_STORE_IS_NATIVE
#define Q_ATOMIC_INT64_FETCH_AND_ADD_IS_NOT_NATIVE
#else
# error "This compiler for i386 is not supported"
#endif
QT_END_NAMESPACE
QT_END_HEADER
#endif // QATOMIC_I386_H

129
src/corelib/arch/qatomic_x86.h
View File

@ -40,8 +40,8 @@
**
****************************************************************************/
#ifndef QATOMIC_X86_64_H
#define QATOMIC_X86_64_H
#ifndef QATOMIC_X86_H
#define QATOMIC_X86_H
#include <QtCore/qgenericatomic.h>
@ -121,7 +121,7 @@ template <typename T> struct QAtomicOps : QBasicAtomicOps<sizeof(T)>
typedef T Type;
};
#if defined(Q_CC_GNU) || defined(Q_CC_INTEL)
#if defined(Q_CC_GNU)
template<> struct QAtomicIntegerTraits<char> { enum { IsInteger = 1 }; };
template<> struct QAtomicIntegerTraits<signed char> { enum { IsInteger = 1 }; };
@ -133,6 +133,34 @@ template<> struct QAtomicIntegerTraits<unsigned long> { enum { IsInteger = 1 };
template<> struct QAtomicIntegerTraits<long long> { enum { IsInteger = 1 }; };
template<> struct QAtomicIntegerTraits<unsigned long long> { enum { IsInteger = 1 }; };
/*
* Guide for the inline assembly below:
*
* x86 instructions are in the form "{opcode}{length} {source}, {destination}",
* where the length is one of the letters "b" (byte), "w" (word, 16-bit), "l"
* (dword, 32-bit), "q" (qword, 64-bit).
*
* In most cases, we can omit the length because it's inferred from one of the
* registers. For example, "xchg %0,%1" doesn't need the length suffix because
* we can only exchange data of the same size and one of the operands must be a
* register.
*
* The exception is the increment and decrement functions, where we add and
* subtract an immediate value (1). For those, we need to specify the length.
* GCC and ICC support the syntax "add%z0 $1, %0", where "%z0" expands to the
* length of the operand. Unfortunately, clang as of 3.0 doesn't support that.
* For that reason, the ref() and deref() functions are rolled out for all
* sizes.
*
* The functions are also rolled out for the 1-byte operations since those
* require a special register constraint "q" to force the compiler to schedule
* one of the 8-bit registers. It's probably a compiler bug that it tries to
* use a register that doesn't exist.
*
* Finally, 64-bit operations are supported via the cmpxchg8b instruction on
* 32-bit processors, via specialisation below.
*/
template<> template<typename T> inline
bool QBasicAtomicOps<1>::ref(T &_q_value)
{
@ -172,19 +200,6 @@ bool QBasicAtomicOps<4>::ref(T &_q_value)
return ret != 0;
}
template<> template<typename T> inline
bool QBasicAtomicOps<8>::ref(T &_q_value)
{
unsigned char ret;
asm volatile("lock\n"
"addq $1, %0\n"
"setne %1"
: "=m" (_q_value), "=qm" (ret)
: "m" (_q_value)
: "memory");
return ret != 0;
}
template<> template <typename T> inline
bool QBasicAtomicOps<1>::deref(T &_q_value)
{
@ -223,19 +238,6 @@ bool QBasicAtomicOps<4>::deref(T &_q_value)
return ret != 0;
}
template<> template <typename T> inline
bool QBasicAtomicOps<8>::deref(T &_q_value)
{
unsigned char ret;
asm volatile("lock\n"
"subq $1, %0\n"
"setne %1"
: "=m" (_q_value), "=qm" (ret)
: "m" (_q_value)
: "memory");
return ret != 0;
}
template<int size> template <typename T> inline
bool QBasicAtomicOps<size>::testAndSetRelaxed(T &_q_value, T expectedValue, T newValue)
{
@ -348,12 +350,73 @@ T QBasicAtomicOps<1>::fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveTy
#define Q_ATOMIC_INT64_FETCH_AND_ADD_IS_ALWAYS_NATIVE
#define Q_ATOMIC_INT64_FETCH_AND_ADD_IS_WAIT_FREE
#else // !Q_CC_INTEL && !Q_CC_GNU
# error "This compiler for x86_64 is not supported"
#endif // Q_CC_GNU || Q_CC_INTEL
#ifdef Q_PROCESSOR_X86_64
// native support for 64-bit types
template<> template<typename T> inline
bool QBasicAtomicOps<8>::ref(T &_q_value)
{
unsigned char ret;
asm volatile("lock\n"
"addq $1, %0\n"
"setne %1"
: "=m" (_q_value), "=qm" (ret)
: "m" (_q_value)
: "memory");
return ret != 0;
}
template<> template <typename T> inline
bool QBasicAtomicOps<8>::deref(T &_q_value)
{
unsigned char ret;
asm volatile("lock\n"
"subq $1, %0\n"
"setne %1"
: "=m" (_q_value), "=qm" (ret)
: "m" (_q_value)
: "memory");
return ret != 0;
}
#else
// i386 architecture, emulate 64-bit support via cmpxchg8b
template <> struct QBasicAtomicOps<8>: QGenericAtomicOps<QBasicAtomicOps<8> >
{
static inline bool isTestAndSetNative() { return true; }
static inline bool isTestAndSetWaitFree() { return true; }
template <typename T> static inline
bool testAndSetRelaxed(T &_q_value, T expectedValue, T newValue)
{
#ifdef __PIC__
# define EBX_reg "r"
# define EBX_load(reg) "xchg " reg ", %%ebx\n"
#else
# define EBX_reg "b"
# define EBX_load(reg)
#endif
quint32 highExpectedValue = quint32(newValue >> 32); // ECX
asm volatile(EBX_load("%3")
"lock\n"
"cmpxchg8b %0\n"
EBX_load("%3")
"sete %%cl\n"
: "+m" (_q_value), "+c" (highExpectedValue), "+&A" (expectedValue)
: EBX_reg (quint32(newValue & 0xffffffff))
: "memory");
// if the comparison failed, expectedValue here contains the current value
return quint8(highExpectedValue) != 0;
#undef EBX_reg
#undef EBX_load
}
};
#endif
#else
# error "This compiler for x86 is not supported"
#endif
QT_END_NAMESPACE
QT_END_HEADER
#endif // QATOMIC_X86_64_H
#endif // QATOMIC_X86_H

2
src/corelib/thread/qbasicatomic.h
View File

@ -80,8 +80,6 @@
# include "QtCore/qatomic_sh4a.h"
#elif defined(Q_PROCESSOR_SPARC)
# include "QtCore/qatomic_sparc.h"
#elif defined(Q_PROCESSOR_X86_32)
# include <QtCore/qatomic_i386.h>
#elif defined(Q_PROCESSOR_X86)
# include <QtCore/qatomic_x86.h>