This got lost in commit b852584556 .
Also augment util/x86simdgen/header so that the header is
automatically included when qsimd_x86_p.h is re-generated.
Change-Id: I3e59b983f78b8c1aced3757e1aa5dceb6d653d97
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
__attribute__((target("arch=xxxx"))) does not work because the compilers
(GCC at least) don't test the CPU features that they are targeting, so
we keep getting "inline failed" compiler errors.
GCC bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90129
Upstream patch: https://github.com/opendcdiag/opendcdiag/pull/59
Change-Id: I6fcda969a9e9427198bffffd16cea09fda4406d2
Reviewed-by: Qt CI Bot <qt_ci_bot@qt-project.org>
Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
I'd been making changes to that and improving it for the past 2 years
without bringing it back into Qt.
The list of features is mostly the same, except:
- removed TSX features
- removed features specific to Xeon Phi processors
- added CET and AVX512FP16 features
- added the bit for hybrid CPU detection
See matching update at https://github.com/opendcdiag/opendcdiag/pull/49
Change-Id: I6fcda969a9e9427198bffffd16ce860b5a38aece
Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
It's not used in tools at all and fits a lot better in global.
Also fix the qsimd_x86* files to have a proper copyright
header.
Change-Id: Id3d8e7cfcd7769a1ca9f3d8cf6d357a31a99ba40
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
We need to use macros because MSVC is a crappy C compiler.
Change-Id: Ieb48f7c0dd0e4e0fb35efffd153b8af62d34ebdf
Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@qt.io>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
... instead of being the bit numbers. This allows us to test more than
one feature at a time with qCpuHasFeature (see commit about the Haswell
architecture features). The drawback is that we won't be able to handle
more than 63 different CPU features, though we're likely quite far from
it (x86 currently has only 36 features).
Change-Id: Iff4151c519c144d580c4fffd153a0acbfd74c2c6
Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@qt.io>
Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI,
AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These
features were found in the "Intel® Architecture Instruction Set
Extensions and Future Features" manual, revision 30. This commit also
adds support for RDPID (already in the main manual) and the Control-flow
Enforcement Technology, which appears in a separate Intel paper.
This new support was done by adding a new generator script so we don't
have to maintain two tables in sync, one in qsimd.cpp with the feature
names, and the other in qsimd_p.h.
Since we now need a lot more bits, it's no longer worth keeping the two
halves of the qt_cpu_features variable mostly similar to the main two
CPUID results. This commit goes back to keeping things in order, like we
used to prior to commit 6a8251a89b (Qt 5.6)
At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ,
AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI.
Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96
Reviewed-by: Edward Welbourne <edward.welbourne@qt.io>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
