cf63b0e1df
This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI,
AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These
features were found in the "Intel® Architecture Instruction Set
Extensions and Future Features" manual, revision 30. This commit also
adds support for RDPID (already in the main manual) and the Control-flow
Enforcement Technology, which appears in a separate Intel paper.
This new support was done by adding a new generator script so we don't
have to maintain two tables in sync, one in qsimd.cpp with the feature
names, and the other in qsimd_p.h.
Since we now need a lot more bits, it's no longer worth keeping the two
halves of the qt_cpu_features variable mostly similar to the main two
CPUID results. This commit goes back to keeping things in order, like we
used to prior to commit 6a8251a89b (Qt 5.6)
At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ,
AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI.
Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96
Reviewed-by: Edward Welbourne <edward.welbourne@qt.io>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
38 lines
1.4 KiB
Plaintext
38 lines
1.4 KiB
Plaintext
# Feature CPUID function Bit Required feature
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sse2 Leaf1EDX 26
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sse3 Leaf1ECX 0
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ssse3 Leaf1ECX 9
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fma Leaf1ECX 12
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sse4.1 Leaf1ECX 19
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sse4.2 Leaf1ECX 20
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movbe Leaf1ECX 22
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popcnt Leaf1ECX 23
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aes Leaf1ECX 25 sse4.2
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avx Leaf1ECX 28
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f16c Leaf1ECX 29
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rdrnd Leaf1ECX 30
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bmi Leaf7_0EBX 3
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hle Leaf7_0EBX 4
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avx2 Leaf7_0EBX 5
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bmi2 Leaf7_0EBX 8
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rtm Leaf7_0EBX 11
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avx512f Leaf7_0EBX 16
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avx512dq Leaf7_0EBX 17
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rdseed Leaf7_0EBX 18
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avx512ifma Leaf7_0EBX 21
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avx512pf Leaf7_0EBX 26
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avx512er Leaf7_0EBX 27
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avx512cd Leaf7_0EBX 28
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sha Leaf7_0EBX 29
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avx512bw Leaf7_0EBX 30
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avx512vl Leaf7_0EBX 31
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avx512vbmi Leaf7_0ECX 1
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avx512vbmi2 Leaf7_0ECX 6
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gfni Leaf7_0ECX 8
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vaes Leaf7_0ECX 9
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avx512vnni Leaf7_0ECX 11
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avx512bitalg Leaf7_0ECX 12
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avx512vpopcntdq Leaf7_0ECX 14
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avx5124nniw Leaf7_0EDX 2
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avx5124fmaps Leaf7_0EDX 3
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