qt5base-lts/config.tests/common/avx512/avx512.cpp
Thiago Macieira a587ad1e50 configure: Add support for detecting AVX512 instructions
Tested on Linux with Clang 3.7, GCC 4.9, 5.1 and 6.0, ICC 16 beta; on OS
X with Clang-XCode 6.4, ICC 16 beta; on Windows with MSVC 2013 and ICC
15. MinGW is not tested.

GCC 4.9:     AVX512F AVX512ER AVX512CD AVX512PF
GCC 5 & 6:   AVX512F AVX512ER AVX512CD AVX512PF AVX512DQ AVX512BW AVX512VL AVX512IFMA AVX512VBMI
Clang 3.7:   AVX512F AVX512ER AVX512CD
Clang-XCode: <none>
ICC 15 & 16: AVX512F AVX512ER AVX512CD AVX512PF AVX512DQ AVX512BW AVX512VL
MSVC 2013:   <none>

Change-Id: Ib306f8f647014b399b87ffff13f1da1b161c31d7
Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@theqtcompany.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
2015-09-25 20:29:22 +00:00

98 lines
3.2 KiB
C++

/****************************************************************************
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** Copyright (C) 2012 Intel Corporation.
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#include <immintrin.h>
#ifndef AVX512WANT
# error ".pro file must define AVX512WANT macro to the AVX-512 feature to be tested"
#endif
// The following checks if __AVXx__ is defined, where x is the value in
// AVX512WANT
#define HAS2(x) __AVX512 ## x ## __
#define HAS(x) HAS2(x)
#if !HAS(AVX512WANT)
# error "Feature not supported"
#endif
int main(int, char**argv)
{
/* AVX512 Foundation */
__m512i i;
__m512d d;
__m512 f;
__mmask16 m = ~1;
i = _mm512_maskz_loadu_epi32(0, argv);
d = _mm512_loadu_pd((double *)argv + 64);
f = _mm512_loadu_ps((float *)argv + 128);
#ifdef __AVX512ER__
/* AVX512 Exponential and Reciprocal */
f = _mm512_exp2a23_round_ps(f, 8);
#endif
#ifdef __AVX512CD__
/* AVX512 Conflict Detection */
i = _mm512_maskz_conflict_epi32(m, i);
#endif
#ifdef __AVX512PF__
/* AVX512 Prefetch */
_mm512_mask_prefetch_i64scatter_pd(argv, 0xf, i, 2, 2);
#endif
#ifdef __AVX512DQ__
/* AVX512 Doubleword and Quadword support */
m = _mm512_movepi32_mask(i);
#endif
#ifdef __AVX512BW__
/* AVX512 Byte and Word support */
i = _mm512_mask_loadu_epi8(i, m, argv - 8);
#endif
#ifdef __AVX512VL__
/* AVX512 Vector Length */
__m256i i2 = _mm256_maskz_loadu_epi32(0, argv);
_mm256_mask_storeu_epi32(argv + 1, m, i2);
#endif
#ifdef __AVX512IFMA__
/* AVX512 Integer Fused Multiply-Add */
i = _mm512_madd52lo_epu64(i, i, i);
#endif
#ifdef __AVX512VBMI__
/* AVX512 Vector Byte Manipulation Instructions */
i = _mm512_permutexvar_epi8(i, i);
#endif
_mm512_mask_storeu_epi64(argv, m, i);
_mm512_mask_storeu_ps(argv + 64, m, f);
_mm512_mask_storeu_pd(argv + 128, m, d);
return 0;
}