735f7e6248
If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
245 lines
6.1 KiB
C++
245 lines
6.1 KiB
C++
/****************************************************************************
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**
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** Copyright (C) 2012 Nokia Corporation and/or its subsidiary(-ies).
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** Copyright (C) 2012 Intel Corporation
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** Contact: http://www.qt-project.org/
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**
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** This file is part of the FOO module of the Qt Toolkit.
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**
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** $QT_BEGIN_LICENSE:LGPL$
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** GNU Lesser General Public License Usage
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** This file may be used under the terms of the GNU Lesser General Public
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** License version 2.1 as published by the Free Software Foundation and
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** appearing in the file LICENSE.LGPL included in the packaging of this
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** file. Please review the following information to ensure the GNU Lesser
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** General Public License version 2.1 requirements will be met:
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** http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html.
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**
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** In addition, as a special exception, Nokia gives you certain additional
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** rights. These rights are described in the Nokia Qt LGPL Exception
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** version 1.1, included in the file LGPL_EXCEPTION.txt in this package.
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**
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** GNU General Public License Usage
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** Alternatively, this file may be used under the terms of the GNU General
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** Public License version 3.0 as published by the Free Software Foundation
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** and appearing in the file LICENSE.GPL included in the packaging of this
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** file. Please review the following information to ensure the GNU General
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** Public License version 3.0 requirements will be met:
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** http://www.gnu.org/copyleft/gpl.html.
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**
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** Other Usage
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** Alternatively, this file may be used in accordance with the terms and
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** conditions contained in a signed written agreement between you and Nokia.
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**
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**
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**
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**
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**
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**
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** $QT_END_LICENSE$
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**
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****************************************************************************/
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#define QGLOBAL_H
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#include "../../src/corelib/global/qprocessordetection.h"
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#include <stdio.h>
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extern const char msg[];
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const char msg[] = "==Qt=magic=Qt== Architecture:"
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#if defined(Q_PROCESSOR_ALPHA)
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"alpha"
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#elif defined(Q_PROCESSOR_ARM)
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"arm"
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#elif defined(Q_PROCESSOR_AVR32)
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"avr32"
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#elif defined(Q_PROCESSOR_BLACKFIN)
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"bfin"
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#elif defined(Q_PROCESSOR_X86_32)
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"i386"
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#elif defined(Q_PROCESSOR_X86_64)
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"x86_64"
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#elif defined(Q_PROCESSOR_IA64)
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"ia64"
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#elif defined(Q_PROCESSOR_MIPS)
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"mips"
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#elif defined(Q_PROCESSOR_POWER)
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"power"
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#elif defined(Q_PROCESSOR_S390)
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"s390"
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#elif defined(Q_PROCESSOR_SH)
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"sh"
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#elif defined(Q_PROCESSOR_SPARC)
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"sparc"
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#else
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"unknown"
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#endif
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;
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extern const char msg2[];
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const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
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// This is the list of features found in GCC or MSVC
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// We don't use all of them, but this is ready for future expansion
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// -- x86 --
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#ifdef __3dNOW__
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// 3dNow!, introduced with the AMD K6-2, discontinued after 2010
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" 3dnow"
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#endif
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#ifdef __3dNOW_A__
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// Athlon
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" 3dnow-a"
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#endif
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#ifdef __ABM__
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// Advanced Bit Manipulation, AMD Barcelona (family 10h)
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" abm"
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#endif
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#ifdef __AES__
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// AES New Instructions, Intel Core-i7 second generation ("Sandy Bridge")
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" aes"
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#endif
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#ifdef __AVX__
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// Advanced Vector Extensions, Intel Core-i7 second generation ("Sandy Bridge")
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" avx"
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#endif
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#ifdef __AVX2__
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// AVX 2, Intel codename "Haswell"
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" avx2"
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#endif
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#ifdef __BMI__
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// Bit Manipulation Instructions 1, Intel codename "Haswell", AMD "Bulldozer 2"
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" bmi"
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#endif
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#ifdef __BMI2__
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// Bit Manipulation Instructions 2, Intel codename "Haswell"
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" bmi2"
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#endif
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#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
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// cmpxchg16b instruction, Intel Pentium 4 64-bit ("Nocona"), AMD Barcelona (family 10h)
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// Notably, this instruction is missing on earlier AMD Athlon 64
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" cx16"
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#endif
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#ifdef __F16C__
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// 16-bit floating point conversion, Intel codename "Ivy Bridge"
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" f16c"
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#endif
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#ifdef __FMA__
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// Fused Multiply-Add with 3 arguments, Intel codename "Haswell", AMD "Bulldozer 2"
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// a.k.a. "FMA3"
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" fma"
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#endif
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#ifdef __FMA4__
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// Fused Multiply-Add with 4 arguments, AMD "Bulldozer"
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" fma4"
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#endif
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#ifdef __FSGSBASE__
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// rdfsgsbase, wrfsgsbase, Intel codename "Ivy Bridge"
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" fsgsbase"
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#endif
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#ifdef __LWP__
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// LWP instructions, AMD "Bulldozer"
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" lwp"
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#endif
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#ifdef __LZCNT__
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// Leading-Zero bit count, Intel codename "Haswell"
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" lzcnt"
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#endif
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#ifdef __MMX__
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// Multimedia Extensions, Pentium MMX, AMD K6-2
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" mmx"
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#endif
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#ifdef __MOVBE__
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// Move Big Endian, Intel Atom & "Haswell"
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" movbe"
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#endif
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#ifdef __NO_SAHF__
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// missing SAHF instruction in 64-bit, up to Intel Pentium 4 64-bit ("Nocona"), AMD Athlon FX
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// Note: the macro is not defined, so this will never show up
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" no-sahf"
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#endif
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#ifdef __PCLMUL__
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// (Packed) Carry-less multiplication, Intel Core-i7 second generation ("Sandy Bridge")
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" pclmul"
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#endif
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#ifdef __POPCNT__
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// Population Count (count of set bits), Intel Core-i7 second generation ("Sandy Bridge")
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" popcnt"
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#endif
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#ifdef __RDRND__
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// Random number generator, Intel codename "Ivy Bridge"
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" rdrnd"
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#endif
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#if defined(__SSE__) || (defined(_M_IX86_FP) && _M_IX86_FP >= 1) || defined(_M_X64)
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// Streaming SIMD Extensions, Intel Pentium III, AMD Athlon
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" sse"
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#endif
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#if defined(__SSE2__) || (defined(_M_IX86_FP) && _M_IX86_FP >= 2) || defined(_M_X64)
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// SSE2, Intel Pentium-M, Intel Pentium 4, AMD Opteron and Athlon 64
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" sse2"
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#endif
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#ifdef __SSE3__
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// SSE3, Intel Pentium 4 "Prescott", AMD Athlon 64 rev E
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" sse3"
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#endif
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#ifdef __SSSE3__
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// Supplemental SSE3, Intel Core 2, AMD "Bulldozer"
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" ssse3"
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#endif
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#ifdef __SSE4A__
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// SSE4a, AMD Barcelona
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" sse4a"
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#endif
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#ifdef __SSE4_1__
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// SSE 4.1, Intel Core-i7 ("Nehalem"), AMD "Bulldozer"
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" sse4.1"
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#endif
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#ifdef __SSE4_2__
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// SSE 4.2, Intel Core-i7 ("Nehalem"), AMD "Bulldozer"
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" sse4.2"
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// Since no processor supports SSE4.2 without 4.1 and since no Intel processor
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// supports SSE4a, define "sse4" to indicate SSE4"
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" sse4"
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#endif
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#ifdef __TBM__
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// TBM, AMD "Bulldozer"
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" tbm"
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#endif
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#ifdef __XOP__
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// XOP, AMD "Bulldozer"
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" xop"
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#endif
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// -- ARM --
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#ifdef __ARM_NEON__
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" neon"
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#endif
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#ifdef __IWMMXT__
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" iwmmxt"
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#endif
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// -- SPARC --
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#ifdef __VIS__
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" vis"
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# if __VIS__ >= 0x200
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" vis2"
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# endif
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# if __VIS__ >= 0x300
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" vis3"
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# endif
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#endif
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// -- MIPS --
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// Wikipedia says there are extensions, but GCC installs no headers
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// -- POWER, PowerPC --
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#ifdef __ALTIVEC__
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" altivec"
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#endif
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"";
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int main()
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{
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puts(msg);
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puts(msg2);
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}
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