Albert Astals Cid c62f717226 Fix signal code generation ... The old code is broken because it was passing signal.outputArgs as inputArgs variable of writeArgList, fix can not be passing signal.outputArgs as outputArgs of writeArgList since that ignores the first of the list, so i added a new function that does the right thing Change-Id: If54484e04880d5dcebfedb9d478ee0e9faf37baa Task-number: QTBUG-21577 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>		2016-10-03 14:01:33 +00:00
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bootstrap	make zlib_dependency auto-add QtCore as a private dep	2016-05-09 12:52:08 +00:00
bootstrap-dbus	consistently put {qt,qml}_{module,plugin} at the end of project files	2016-03-07 14:09:49 +00:00
moc	moc: fix infinite loop over malformed input	2016-07-20 06:56:40 +00:00
qdbuscpp2xml	Reduce allocations by using reserve()	2016-02-07 16:50:26 +00:00
qdbusxml2cpp	Fix signal code generation	2016-10-03 14:01:33 +00:00
qlalr	Remove empty first lines of files.	2016-04-06 18:26:26 +00:00
rcc	rcc compiler with -list on Windows (newline symbols)	2016-04-08 19:15:26 +00:00
uic	uic: generate translate calls with Q_NULLPTR instead of 0	2016-09-03 05:07:50 +00:00