fe6dc9dc85
Adds runtime CPU detection for Windows and macOS, and switches feature detection of AES to runtime like for x86, So far only on ARM64, since gcc doesn't do function versioning on ARM32, but clang can, so it could be added later. Change-Id: Ibe5d60f48cdae3e366a8ecd6263534ba2b09b131 Reviewed-by: Tor Arne Vestbø <tor.arne.vestbo@qt.io> Reviewed-by: Alexandru Croitor <alexandru.croitor@qt.io>
331 lines
9.1 KiB
C++
331 lines
9.1 KiB
C++
/****************************************************************************
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**
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** Copyright (C) 2016 The Qt Company Ltd.
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** Copyright (C) 2016 Intel Corporation.
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** Contact: https://www.qt.io/licensing/
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**
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** This file is part of the FOO module of the Qt Toolkit.
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**
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** $QT_BEGIN_LICENSE:LGPL$
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** Commercial License Usage
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** Licensees holding valid commercial Qt licenses may use this file in
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** accordance with the commercial license agreement provided with the
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** Software or, alternatively, in accordance with the terms contained in
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** a written agreement between you and The Qt Company. For licensing terms
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** and conditions see https://www.qt.io/terms-conditions. For further
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** information use the contact form at https://www.qt.io/contact-us.
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**
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** GNU Lesser General Public License Usage
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** Alternatively, this file may be used under the terms of the GNU Lesser
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** General Public License version 3 as published by the Free Software
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** Foundation and appearing in the file LICENSE.LGPL3 included in the
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** packaging of this file. Please review the following information to
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** ensure the GNU Lesser General Public License version 3 requirements
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** will be met: https://www.gnu.org/licenses/lgpl-3.0.html.
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**
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** GNU General Public License Usage
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** Alternatively, this file may be used under the terms of the GNU
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** General Public License version 2.0 or (at your option) the GNU General
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** Public license version 3 or any later version approved by the KDE Free
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** Qt Foundation. The licenses are as published by the Free Software
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** Foundation and appearing in the file LICENSE.GPL2 and LICENSE.GPL3
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** included in the packaging of this file. Please review the following
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** information to ensure the GNU General Public License requirements will
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** be met: https://www.gnu.org/licenses/gpl-2.0.html and
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** https://www.gnu.org/licenses/gpl-3.0.html.
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**
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** $QT_END_LICENSE$
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**
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****************************************************************************/
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#define QGLOBAL_H
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#include "../../src/corelib/global/archdetect.cpp"
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#include <stdio.h>
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extern const char msg[];
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const char msg[] = "==Qt=magic=Qt== Architecture:" ARCH_PROCESSOR;
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extern const char msg2[];
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const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
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// This is the list of features found in GCC or MSVC
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// We don't use all of them, but this is ready for future expansion
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// -- x86 --
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#ifdef __3dNOW__
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// 3dNow!, introduced with the AMD K6-2, discontinued after 2010
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" 3dnow"
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#endif
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#ifdef __3dNOW_A__
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// Athlon
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" 3dnow-a"
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#endif
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#ifdef __ABM__
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// Advanced Bit Manipulation, AMD Barcelona (family 10h)
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" abm"
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#endif
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#ifdef __ADX__
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// Multi-Precision Add-Carry Instruction Extensions, Intel Core 5th generation ("Broadwell")
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" adx"
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#endif
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#ifdef __AES__
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// AES New Instructions, Intel Core-i7 second generation ("Sandy Bridge")
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" aes"
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#endif
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#ifdef __AVX__
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// Advanced Vector Extensions, Intel Core-i7 second generation ("Sandy Bridge")
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" avx"
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#endif
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#ifdef __AVX2__
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// AVX 2, Intel Core 4th Generation ("Haswell")
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" avx2"
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#endif
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#ifdef __AVX512F__
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// AVX512 Foundation, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake")
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" avx512f"
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#endif
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#ifdef __AVX512CD__
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// AVX512 Conflict Detection, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake")
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" avx512cd"
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#endif
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#ifdef __AVX512DQ__
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// AVX512 Double & Quadword, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake")
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" avx512dq"
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#endif
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#ifdef __AVX512BW__
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// AVX512 Byte & Word, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake")
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" avx512bw"
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#endif
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#ifdef __AVX512ER__
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// AVX512 Exponentiation & Reciprocal, Intel Xeon Phi codename "Knights Landing"
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" avx512ef"
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#endif
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#ifdef __AVX512PF__
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// AVX512 Prefetch, Intel Xeon Phi codename "Knights Landing"
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" avx512pf"
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#endif
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#ifdef __AVX512VL__
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// AVX512 Vector Length, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake")
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" avx512vl"
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#endif
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#ifdef __AVX512IFMA__
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// AVX512 Integer Fused Multiply-Add, Intel processor codename "Cannonlake"
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" avx512ifma"
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#endif
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#ifdef __AVX512VBMI__
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// AVX512 Vector Byte Manipulation Instructions, Intel processor codename "Cannonlake"
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" avx512vbmi"
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#endif
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#ifdef __AVX512VBMI2__
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// AVX512 Vector Byte Manipulation Instructions #2, Intel processor codename "Ice Lake"
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" avx512vbmi2"
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#endif
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#ifdef __AVX512VPOPCNTDQ__
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// AVX512 Vector Population Count Double & Quad, Future Intel Xeon Phi processor codename "Knights Mill", Intel processor codename "Ice Lake"
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" avx512vpopcntdq"
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#endif
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#ifdef __AVX5124FMAPS__
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// AVX512 4-iteration Fused Multiply Accumulation Packed Single, Future Intel Xeon Phi processor codename "Knights Mill"
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" avx5124fmaps"
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#endif
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#ifdef __AVX5124VNNIW__
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// AVX512 4-iteration Vector Neural Network Instructions Word, Future Intel Xeon Phi processor codename "Knights Mill"
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" avx5124vnniw"
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#endif
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#ifdef __BMI__
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// Bit Manipulation Instructions 1, Intel Core 4th Generation ("Haswell"), AMD "Bulldozer 2"
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" bmi"
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#endif
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#ifdef __BMI2__
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// Bit Manipulation Instructions 2, Intel Core 4th Generation ("Haswell")
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" bmi2"
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#endif
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#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
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// cmpxchg16b instruction, Intel Pentium 4 64-bit ("Nocona"), AMD Barcelona (family 10h)
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// Notably, this instruction is missing on earlier AMD Athlon 64
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" cx16"
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#endif
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#ifdef __F16C__
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// 16-bit floating point conversion, Intel Core 3rd Generation ("Ivy Bridge")
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" f16c"
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#endif
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#ifdef __FMA__
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// Fused Multiply-Add with 3 arguments, Intel Core 4th Generation ("Haswell"), AMD "Bulldozer 2"
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// a.k.a. "FMA3"
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" fma"
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#endif
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#ifdef __FMA4__
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// Fused Multiply-Add with 4 arguments, AMD "Bulldozer"
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" fma4"
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#endif
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#ifdef __FSGSBASE__
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// rdfsgsbase, wrfsgsbase, Intel Core 3rd Generation ("Ivy Bridge")
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" fsgsbase"
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#endif
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#ifdef __GFNI__
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// Galois Field new instructions, Intel processor codename "Ice Lake"
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" gfni"
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#endif
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#ifdef __IBT__
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// Indirect Branch Tracking, Intel processor TBA
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" ibt"
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#endif
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#ifdef __LWP__
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// LWP instructions, AMD "Bulldozer"
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" lwp"
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#endif
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#ifdef __LZCNT__
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// Leading-Zero bit count, Intel Core 4th Generation ("Haswell")
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" lzcnt"
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#endif
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#ifdef __MMX__
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// Multimedia Extensions, Pentium MMX, AMD K6-2
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" mmx"
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#endif
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#ifdef __MOVBE__
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// Move Big Endian, Intel Atom & "Haswell"
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" movbe"
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#endif
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#ifdef __MPX__
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// Memory Protection Extensions, Intel Core processor codename "Skylake"
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" mpx"
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#endif
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#ifdef __NO_SAHF__
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// missing SAHF instruction in 64-bit, up to Intel Pentium 4 64-bit ("Nocona"), AMD Athlon FX
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// Note: the macro is not defined, so this will never show up
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" no-sahf"
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#endif
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#ifdef __PCLMUL__
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// (Packed) Carry-less multiplication, Intel Core-i7 second generation ("Sandy Bridge")
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" pclmul"
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#endif
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#ifdef __POPCNT__
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// Population Count (count of set bits), Intel Core-i7 second generation ("Sandy Bridge")
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" popcnt"
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#endif
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#ifdef __PREFETCHWT1__
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// Prefetch data for writing with T1 hint, Intel processor TBA
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" prefetchwt1"
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#endif
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#ifdef __PRFCHW__
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// Prefetch data for writing, Intel Core 5th Generation ("Broadwell")
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" prfchw"
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#endif
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#ifdef __RDPID__
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// Read Processor ID, Intel processors codename "Ice Lake" and "Goldmont Plus"
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" rdpid"
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#endif
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#ifdef __RDRND__
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// Random number generator, Intel Core 3rd Generation ("Ivy Bridge")
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" rdrnd"
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#endif
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#ifdef __RDSEED__
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// Random number generator, Intel Core 5th Generation ("Broadwell")
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" rdseed"
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#endif
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#ifdef __RTM__
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// Restricted Transactional Memory, Intel Core 4th Generation ("Haswell")
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" rtm"
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#endif
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#ifdef __SHA__
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// SHA-1 and SHA-256 instructions, Intel processors codename "Cannon Lake" and "Goldmont"
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" sha"
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#endif
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#ifdef __SHSTK__
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// Shadow stack, Intel processor TBA
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" shstk"
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#endif
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#if defined(__SSE__) || (defined(_M_IX86_FP) && _M_IX86_FP >= 1) || defined(_M_X64)
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// Streaming SIMD Extensions, Intel Pentium III, AMD Athlon
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" sse"
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#endif
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#if defined(__SSE2__) || (defined(_M_IX86_FP) && _M_IX86_FP >= 2) || defined(_M_X64)
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// SSE2, Intel Pentium-M, Intel Pentium 4, AMD Opteron and Athlon 64
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" sse2"
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#endif
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#ifdef __SSE3__
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// SSE3, Intel Pentium 4 "Prescott", AMD Athlon 64 rev E
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" sse3"
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#endif
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#ifdef __SSSE3__
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// Supplemental SSE3, Intel Core 2 ("Merom"), AMD "Bulldozer"
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" ssse3"
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#endif
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#ifdef __SSE4A__
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// SSE4a, AMD Barcelona
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" sse4a"
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#endif
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#ifdef __SSE4_1__
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// SSE 4.1, Intel Core2 45nm shrink ("Penryn"), AMD "Bulldozer"
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" sse4.1"
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#endif
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#ifdef __SSE4_2__
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// SSE 4.2, Intel Core-i7 ("Nehalem"), AMD "Bulldozer"
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" sse4.2"
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// Since no processor supports SSE4.2 without 4.1 and since no Intel processor
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// supports SSE4a, define "sse4" to indicate SSE4"
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" sse4"
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#endif
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#ifdef __TBM__
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// TBM, AMD "Bulldozer"
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" tbm"
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#endif
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#ifdef __XOP__
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// XOP, AMD "Bulldozer"
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" xop"
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#endif
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// -- ARM --
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#if defined(__ARM_NEON) || defined(__ARM_NEON__)
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" neon"
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#endif
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#ifdef __IWMMXT__
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" iwmmxt"
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#endif
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#ifdef __ARM_FEATURE_CRC32
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" crc32"
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#endif
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#ifdef __ARM_FEATURE_CRYPTO
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" crypto"
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#endif
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// -- SPARC --
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#ifdef __VIS__
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" vis"
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# if __VIS__ >= 0x200
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" vis2"
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# endif
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# if __VIS__ >= 0x300
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" vis3"
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# endif
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#endif
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// -- MIPS --
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# if __mips_dsp
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" dsp"
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# endif
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# if __mips_dspr2
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" dspr2"
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# endif
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// -- POWER, PowerPC --
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#ifdef __ALTIVEC__
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" altivec"
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#endif
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#ifdef __SPE__
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" spe"
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#endif
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#ifdef __VSX__
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" vsx"
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#endif
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"";
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extern const char msg3[];
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const char msg3[] = "==Qt=magic=Qt== Build-ABI:" ARCH_FULL;
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int main()
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{
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puts(msg);
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puts(msg2);
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puts(msg3);
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}
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