align f16 buffers in SkRasterPipeline_tail test
The load_f16 and store_f16 stages are assuming they can load each pixel at a time with 8 byte alignment, but as declared the buffers are only guaranteed 2 byte alignment. Bug: skia:7497 Change-Id: I47b29f13b48f90d2b15540979c3d87ba25dcc506 Reviewed-on: https://skia-review.googlesource.com/110321 Reviewed-by: Kevin Lubick <kjlubick@google.com> Commit-Queue: Mike Klein <mtklein@chromium.org>
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@ -496,7 +496,6 @@
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"GrShape",
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"--match",
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"~readpixels",
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"~SkRasterPipeline_tail",
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"~GM_animated-image-blurs",
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"~verylarge",
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"~ImageFilterBlurLargeImage",
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@ -599,7 +599,6 @@
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"~imageblur2",
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"~animated-image-blurs",
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"~readpixels",
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"~SkRasterPipeline_tail",
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"~GM_animated-image-blurs",
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"~verylarge",
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"~ImageFilterBlurLargeImage",
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@ -528,7 +528,6 @@ def dm_flags(api, bot):
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match.append('~animated-image-blurs')
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# skia:7497
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match.append('~readpixels') # dies with "Caught signal 7 [Bus error]"
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match.append('~SkRasterPipeline_tail')
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# Blacklisted to avoid OOM (we see DM just end with "broken pipe")
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match.append('~GM_animated-image-blurs')
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match.append('~verylarge')
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@ -137,13 +137,13 @@ DEF_TEST(SkRasterPipeline_tail, r) {
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}
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{
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uint16_t data[][4] = {
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alignas(8) uint16_t data[][4] = {
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{h(00), h(01), h(02), h(03)},
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{h(10), h(11), h(12), h(13)},
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{h(20), h(21), h(22), h(23)},
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{h(30), h(31), h(32), h(33)},
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};
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uint16_t buffer[4][4];
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alignas(8) uint16_t buffer[4][4];
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SkJumper_MemoryCtx src = { &data[0][0], 0 },
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dst = { &buffer[0][0], 0 };
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