align f16 buffers in SkRasterPipeline_tail test

The load_f16 and store_f16 stages are assuming they can load
each pixel at a time with 8 byte alignment, but as declared
the buffers are only guaranteed 2 byte alignment.

Bug: skia:7497

Change-Id: I47b29f13b48f90d2b15540979c3d87ba25dcc506
Reviewed-on: https://skia-review.googlesource.com/110321
Reviewed-by: Kevin Lubick <kjlubick@google.com>
Commit-Queue: Mike Klein <mtklein@chromium.org>
This commit is contained in:
Mike Klein 2018-02-26 13:34:21 -05:00 committed by Skia Commit-Bot
parent 8385a8a44b
commit 0bf89269eb
4 changed files with 2 additions and 5 deletions

View File

@ -496,7 +496,6 @@
"GrShape",
"--match",
"~readpixels",
"~SkRasterPipeline_tail",
"~GM_animated-image-blurs",
"~verylarge",
"~ImageFilterBlurLargeImage",

View File

@ -599,7 +599,6 @@
"~imageblur2",
"~animated-image-blurs",
"~readpixels",
"~SkRasterPipeline_tail",
"~GM_animated-image-blurs",
"~verylarge",
"~ImageFilterBlurLargeImage",

View File

@ -528,7 +528,6 @@ def dm_flags(api, bot):
match.append('~animated-image-blurs')
# skia:7497
match.append('~readpixels') # dies with "Caught signal 7 [Bus error]"
match.append('~SkRasterPipeline_tail')
# Blacklisted to avoid OOM (we see DM just end with "broken pipe")
match.append('~GM_animated-image-blurs')
match.append('~verylarge')

View File

@ -137,13 +137,13 @@ DEF_TEST(SkRasterPipeline_tail, r) {
}
{
uint16_t data[][4] = {
alignas(8) uint16_t data[][4] = {
{h(00), h(01), h(02), h(03)},
{h(10), h(11), h(12), h(13)},
{h(20), h(21), h(22), h(23)},
{h(30), h(31), h(32), h(33)},
};
uint16_t buffer[4][4];
alignas(8) uint16_t buffer[4][4];
SkJumper_MemoryCtx src = { &data[0][0], 0 },
dst = { &buffer[0][0], 0 };