AuroraMiddleware/skia2
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Add build targets for advanced Intel instruction sets (1 of 3).

Browse Source 
CL (1 of 3) adds empty lists in our .gypi,
and builds the files in those empty lists with the appropriate flags.

CL (2 of 3) will have Chrome's GYP and GN files read these lists,
and build them with the appropriate flags.

CL (3 of 3) will add runtime detection and stub files to the lists
with empty Init_sse42(), Init_avx(), Init_avx2() methods.

After that, we should be able to use SSE 4.2, AVX, and AVX2 if desired.

Some motivation:
  - SSE 4.2 adds some sweet string-oriented methods that
    can help us write fast high quality 32-bit hashes.
  - AVX is SSE doubled, e.g. 8 floats or two SkPMFloat at a time.
  - AVX2 is SSE2 doubled, e.g. 8 pixels at a time.

BUG=skia:4117

Review URL: https://codereview.chromium.org/1290423007
This commit is contained in:
mtklein 2015-08-24 10:32:02 -07:00 committed by Commit bot
parent 26db32bc9a
commit 5141d90796
3 changed files with 75 additions and 5 deletions
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56
gyp/opts.gyp
View File

@ -34,7 +34,7 @@
'conditions': [
[ '"x86" in skia_arch_type and skia_os != "ios"', {
'cflags': [ '-msse2' ],
'dependencies': [ 'opts_ssse3', 'opts_sse41' ],
'dependencies': [ 'opts_ssse3', 'opts_sse41', 'opts_sse42', 'opts_avx', 'opts_avx2' ],
'sources': [ '<@(sse2_sources)' ],
}],
@ -128,6 +128,60 @@
}],
],
},
{
'target_name': 'opts_sse42',
'product_name': 'skia_opts_sse42',
'type': 'static_library',
'standalone_static_library': 1,
'dependencies': [ 'core.gyp:*' ],
'include_dirs': [
'../include/private',
'../src/core',
'../src/utils',
],
'sources': [ '<@(sse42_sources)' ],
'conditions': [
[ 'skia_os == "win"', { 'defines' : [ 'SK_CPU_SSE_LEVEL=42' ], }],
[ 'not skia_android_framework', { 'cflags': [ '-msse4.2' ], }],
[ 'skia_os == "mac"', { 'xcode_settings': { 'GCC_ENABLE_SSE42_EXTENSIONS': 'YES' }, }],
],
},
{
'target_name': 'opts_avx',
'product_name': 'skia_opts_avx',
'type': 'static_library',
'standalone_static_library': 1,
'dependencies': [ 'core.gyp:*' ],
'include_dirs': [
'../include/private',
'../src/core',
'../src/utils',
],
'sources': [ '<@(avx_sources)' ],
'conditions': [
[ 'skia_os == "win"', { 'defines' : [ 'SK_CPU_SSE_LEVEL=51' ], }],
[ 'not skia_android_framework', { 'cflags': [ '-mavx' ], }],
[ 'skia_os == "mac"', { 'xcode_settings': { 'OTHER_CFLAGS': [ '-mavx' ] }, }],
],
},
{
'target_name': 'opts_avx2',
'product_name': 'skia_opts_avx2',
'type': 'static_library',
'standalone_static_library': 1,
'dependencies': [ 'core.gyp:*' ],
'include_dirs': [
'../include/private',
'../src/core',
'../src/utils',
],
'sources': [ '<@(avx2_sources)' ],
'conditions': [
[ 'skia_os == "win"', { 'defines' : [ 'SK_CPU_SSE_LEVEL=52' ], }],
[ 'not skia_android_framework', { 'cflags': [ '-mavx2' ], }],
[ 'skia_os == "mac"', { 'xcode_settings': { 'OTHER_CFLAGS': [ '-mavx2' ] }, }],
],
},
{
'target_name': 'opts_neon',
'product_name': 'skia_opts_neon',

6
gyp/opts.gypi
View File

@ -52,4 +52,10 @@
'<(skia_src_path)/opts/SkBlitRow_opts_SSE4.cpp',
'<(skia_src_path)/opts/SkOpts_sse41.cpp',
],
'sse42_sources': [
],
'avx_sources': [
],
'avx2_sources': [
],
}

18
include/core/SkPreConfig.h
View File

@ -114,12 +114,18 @@
#define SK_CPU_SSE_LEVEL_SSSE3 31
#define SK_CPU_SSE_LEVEL_SSE41 41
#define SK_CPU_SSE_LEVEL_SSE42 42
#define SK_CPU_SSE_LEVEL_AVX 51
#define SK_CPU_SSE_LEVEL_AVX2 52
// Are we in GCC?
#ifndef SK_CPU_SSE_LEVEL
// These checks must be done in descending order to ensure we set the highest
// available SSE level.
#if defined(__SSE4_2__)
#if defined(__AVX2__)
#define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_AVX2
#elif defined(__AVX__)
#define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_AVX
#elif defined(__SSE4_2__)
#define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE42
#elif defined(__SSE4_1__)
#define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE41
@ -136,9 +142,13 @@
#ifndef SK_CPU_SSE_LEVEL
// These checks must be done in descending order to ensure we set the highest
// available SSE level. 64-bit intel guarantees at least SSE2 support.
#if defined(_M_X64) || defined(_M_AMD64)
#define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE2
#elif defined (_M_IX86_FP)
#if defined(__AVX2__)
#define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_AVX2
#elif defined(__AVX__)
#define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_AVX
#elif defined(_M_X64) || defined(_M_AMD64)
#define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE2
#elif defined(_M_IX86_FP)
#if _M_IX86_FP >= 2
#define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE2
#elif _M_IX86_FP == 1