Roll skia/third_party/skcms 36eeb1311a72..0da672fc2c69 (1 commits)
https://skia.googlesource.com/skcms.git/+log/36eeb1311a72..0da672fc2c69 2019-04-09 mtklein@google.com runtime detection for AVX-512 The AutoRoll server is located here: https://autoroll.skia.org/r/skcms-skia-autoroll Documentation for the AutoRoller is here: https://skia.googlesource.com/buildbot/+/master/autoroll/README.md If the roll is causing failures, please contact the current sheriff, who should be CC'd on the roll, and stop the roller if necessary. CQ_INCLUDE_TRYBOTS=luci.chromium.try:linux-blink-rel TBR=egdaniel@google.com Change-Id: I03188337dea03591fecfae9b3e93a5c4a8bd3725 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/206880 Reviewed-by: skia-autoroll <skia-autoroll@skia-public.iam.gserviceaccount.com> Commit-Queue: skia-autoroll <skia-autoroll@skia-public.iam.gserviceaccount.com>
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skia-autoroll
Skia Commit-Bot
parent
a519999fa5
commit
ba6087c8b7
199
third_party/skcms/skcms.cc
vendored
199
third_party/skcms/skcms.cc
vendored
@ -17,6 +17,19 @@
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#include <arm_neon.h>
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#elif defined(__SSE__)
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#include <immintrin.h>
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#if defined(__clang__)
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// That #include <immintrin.h> is usually enough, but Clang's headers
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// "helpfully" skip including the whole kitchen sink when _MSC_VER is
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// defined, because lots of programs on Windows would include that and
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// it'd be a lot slower. But we want all those headers included so we
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// can use their features after runtime checks later.
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#include <smmintrin.h>
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#include <avxintrin.h>
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#include <avx2intrin.h>
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#include <avx512fintrin.h>
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#include <avx512dqintrin.h>
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#endif
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#endif
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// sizeof(x) will return size_t, which is 32-bit on some machines and 64-bit on others.
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@ -1864,80 +1877,127 @@ namespace baseline {
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#if !defined(SKCMS_PORTABLE) && \
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(( defined(__clang__) && __clang_major__ >= 5) || \
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(!defined(__clang__) && defined(__GNUC__))) \
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&& defined(__x86_64__) && !defined(__AVX2__)
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&& defined(__x86_64__)
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#if defined(__clang__)
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#pragma clang attribute push(__attribute__((target("avx2,f16c"))), apply_to=function)
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#elif defined(__GNUC__)
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#pragma GCC push_options
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#pragma GCC target("avx2,f16c")
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#if !defined(__AVX2__)
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#if defined(__clang__)
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#pragma clang attribute push(__attribute__((target("avx2,f16c"))), apply_to=function)
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#elif defined(__GNUC__)
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#pragma GCC push_options
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#pragma GCC target("avx2,f16c")
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#endif
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namespace hsw {
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#define USING_AVX
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#define USING_AVX_F16C
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#define USING_AVX2
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#define N 8
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using F = Vec<N,float>;
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using I32 = Vec<N,int32_t>;
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using U64 = Vec<N,uint64_t>;
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using U32 = Vec<N,uint32_t>;
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using U16 = Vec<N,uint16_t>;
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using U8 = Vec<N,uint8_t>;
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#include "src/Transform_inl.h"
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// src/Transform_inl.h will undefine USING_* for us.
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#undef N
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}
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#if defined(__clang__)
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#pragma clang attribute pop
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#elif defined(__GNUC__)
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#pragma GCC pop_options
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#endif
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#define TEST_FOR_HSW
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#endif
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namespace hsw {
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#define USING_AVX
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#define USING_AVX_F16C
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#define USING_AVX2
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#define N 8
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using F = Vec<N,float>;
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using I32 = Vec<N,int32_t>;
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using U64 = Vec<N,uint64_t>;
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using U32 = Vec<N,uint32_t>;
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using U16 = Vec<N,uint16_t>;
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using U8 = Vec<N,uint8_t>;
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#if !defined(__AVX512F__)
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#if defined(__clang__)
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#pragma clang attribute push(__attribute__((target("avx512f,avx512dq,avx512cd,avx512bw,avx512vl"))), apply_to=function)
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#elif defined(__GNUC__)
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#pragma GCC push_options
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#pragma GCC target("avx512f,avx512dq,avx512cd,avx512bw,avx512vl")
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#endif
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#include "src/Transform_inl.h"
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namespace skx {
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#define USING_AVX512F
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#define N 16
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using F = Vec<N,float>;
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using I32 = Vec<N,int32_t>;
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using U64 = Vec<N,uint64_t>;
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using U32 = Vec<N,uint32_t>;
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using U16 = Vec<N,uint16_t>;
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using U8 = Vec<N,uint8_t>;
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// src/Transform_inl.h will undefine USING_* for us.
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#undef N
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}
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#include "src/Transform_inl.h"
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#if defined(__clang__)
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#pragma clang attribute pop
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#elif defined(__GNUC__)
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#pragma GCC pop_options
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// src/Transform_inl.h will undefine USING_* for us.
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#undef N
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}
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#if defined(__clang__)
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#pragma clang attribute pop
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#elif defined(__GNUC__)
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#pragma GCC pop_options
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#endif
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#define TEST_FOR_SKX
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#endif
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#define TEST_FOR_HSW
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#if defined(TEST_FOR_HSW) || defined(TEST_FOR_SKX)
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enum class CpuType { None, HSW, SKX };
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static CpuType cpu_type() {
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static const CpuType type = []{
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// See http://www.sandpile.org/x86/cpuid.htm
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static bool hsw_ok() {
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static const bool ok = []{
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// See http://www.sandpile.org/x86/cpuid.htm
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// First, a basic cpuid(1) lets us check prerequisites for HSW, SKX.
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uint32_t eax, ebx, ecx, edx;
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__asm__ __volatile__("cpuid" : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
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: "0"(1), "2"(0));
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if ((edx & (1u<<25)) && // SSE
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(edx & (1u<<26)) && // SSE2
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(ecx & (1u<< 0)) && // SSE3
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(ecx & (1u<< 9)) && // SSSE3
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(ecx & (1u<<12)) && // FMA (N.B. not used, avoided even)
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(ecx & (1u<<19)) && // SSE4.1
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(ecx & (1u<<20)) && // SSE4.2
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(ecx & (1u<<26)) && // XSAVE
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(ecx & (1u<<27)) && // OSXSAVE
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(ecx & (1u<<28)) && // AVX
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(ecx & (1u<<29))) { // F16C
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// First, a basic cpuid(1).
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uint32_t eax, ebx, ecx, edx;
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__asm__ __volatile__("cpuid" : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
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: "0"(1), "2"(0));
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// Call cpuid(7) to check for AVX2 and AVX-512 bits.
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__asm__ __volatile__("cpuid" : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
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: "0"(7), "2"(0));
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// eax from xgetbv(0) will tell us whether XMM, YMM, and ZMM state is saved.
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uint32_t xcr0, dont_need_edx;
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__asm__ __volatile__("xgetbv" : "=a"(xcr0), "=d"(dont_need_edx) : "c"(0));
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// Sanity check for prerequisites.
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if ((edx & (1<<25)) != (1<<25)) { return false; } // SSE
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if ((edx & (1<<26)) != (1<<26)) { return false; } // SSE2
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if ((ecx & (1<< 0)) != (1<< 0)) { return false; } // SSE3
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if ((ecx & (1<< 9)) != (1<< 9)) { return false; } // SSSE3
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if ((ecx & (1<<19)) != (1<<19)) { return false; } // SSE4.1
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if ((ecx & (1<<20)) != (1<<20)) { return false; } // SSE4.2
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if ((ecx & (3<<26)) != (3<<26)) { return false; } // XSAVE + OSXSAVE
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{
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uint32_t eax_xgetbv, edx_xgetbv;
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__asm__ __volatile__("xgetbv" : "=a"(eax_xgetbv), "=d"(edx_xgetbv) : "c"(0));
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if ((eax_xgetbv & (3<<1)) != (3<<1)) { return false; } // XMM+YMM state saved?
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}
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if ((ecx & (1<<28)) != (1<<28)) { return false; } // AVX
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if ((ecx & (1<<29)) != (1<<29)) { return false; } // F16C
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if ((ecx & (1<<12)) != (1<<12)) { return false; } // FMA (TODO: not currently used)
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// Call cpuid(7) to check for our final AVX2 feature bit!
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__asm__ __volatile__("cpuid" : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
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: "0"(7), "2"(0));
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if ((ebx & (1<< 5)) != (1<< 5)) { return false; } // AVX2
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return true;
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}();
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return ok;
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}
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if ((xcr0 & (1u<<1)) && // XMM register state saved?
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(xcr0 & (1u<<2)) && // YMM register state saved?
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(ebx & (1u<<5))) { // AVX2
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// At this point we're at least HSW. Continue checking for SKX.
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if ((xcr0 & (1u<< 5)) && // Opmasks state saved?
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(xcr0 & (1u<< 6)) && // First 16 ZMM registers saved?
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(xcr0 & (1u<< 7)) && // High 16 ZMM registers saved?
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(ebx & (1u<<16)) && // AVX512F
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(ebx & (1u<<17)) && // AVX512DQ
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(ebx & (1u<<28)) && // AVX512CD
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(ebx & (1u<<30)) && // AVX512BW
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(ebx & (1u<<31))) { // AVX512VL
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return CpuType::SKX;
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}
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return CpuType::HSW;
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}
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}
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return CpuType::None;
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}();
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return type;
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}
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#endif
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#endif
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@ -2260,7 +2320,18 @@ bool skcms_TransformWithPalette(const void* src,
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auto run = baseline::run_program;
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#if defined(TEST_FOR_HSW)
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if (hsw_ok()) { run = hsw::run_program; }
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switch (cpu_type()) {
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case CpuType::None: break;
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case CpuType::HSW: run = hsw::run_program; break;
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case CpuType::SKX: run = hsw::run_program; break;
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}
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#endif
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#if defined(TEST_FOR_SKX)
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switch (cpu_type()) {
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case CpuType::None: break;
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case CpuType::HSW: break;
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case CpuType::SKX: run = skx::run_program; break;
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}
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#endif
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run(program, arguments, (const char*)src, (char*)dst, n, src_bpp,dst_bpp);
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return true;
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18
third_party/skcms/src/Transform_inl.h
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18
third_party/skcms/src/Transform_inl.h
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@ -43,6 +43,9 @@
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#if !defined(USING_AVX2) && defined(USING_AVX) && defined(__AVX2__)
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#define USING_AVX2
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#endif
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#if !defined(USING_AVX512F) && N == 16 && defined(__AVX512F__)
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#define USING_AVX512F
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#endif
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// Similar to the AVX+ features, we define USING_NEON and USING_NEON_F16C.
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// This is more for organizational clarity... skcms.cc doesn't force these.
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@ -138,7 +141,7 @@ SI T if_then_else(I32 cond, T t, T e) {
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SI F F_from_Half(U16 half) {
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#if defined(USING_NEON_F16C)
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return vcvt_f32_f16((float16x4_t)half);
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#elif defined(__AVX512F__)
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#elif defined(USING_AVX512F)
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return (F)_mm512_cvtph_ps((__m256i)half);
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#elif defined(USING_AVX_F16C)
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typedef int16_t __attribute__((vector_size(16))) I16;
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@ -165,7 +168,7 @@ SI F F_from_Half(U16 half) {
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SI U16 Half_from_F(F f) {
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#if defined(USING_NEON_F16C)
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return (U16)vcvt_f16_f32(f);
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#elif defined(__AVX512F__)
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#elif defined(USING_AVX512F)
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return (U16)_mm512_cvtps_ph((__m512 )f, _MM_FROUND_CUR_DIRECTION );
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#elif defined(USING_AVX_F16C)
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return (U16)__builtin_ia32_vcvtps2ph256(f, 0x04/*_MM_FROUND_CUR_DIRECTION*/);
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@ -206,8 +209,12 @@ SI F floor_(F x) {
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return floorf_(x);
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#elif defined(__aarch64__)
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return vrndmq_f32(x);
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#elif defined(__AVX512F__)
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return _mm512_floor_ps(x);
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#elif defined(USING_AVX512F)
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// Clang's _mm512_floor_ps() passes its mask as -1, not (__mmask16)-1,
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// and integer santizer catches that this implicit cast changes the
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// value from -1 to 65535. We'll cast manually to work around it.
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// Read this as `return _mm512_floor_ps(x)`.
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return _mm512_mask_floor_ps(x, (__mmask16)-1, x);
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#elif defined(USING_AVX)
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return __builtin_ia32_roundps256(x, 0x01/*_MM_FROUND_FLOOR*/);
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#elif defined(__SSE4_1__)
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@ -1238,6 +1245,9 @@ static void run_program(const Op* program, const void** arguments,
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#if defined(USING_AVX2)
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#undef USING_AVX2
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#endif
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#if defined(USING_AVX512F)
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#undef USING_AVX512F
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#endif
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#if defined(USING_NEON)
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#undef USING_NEON
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2
third_party/skcms/version.sha1
vendored
2
third_party/skcms/version.sha1
vendored
@ -1 +1 @@
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36eeb1311a720755fb065f46987158e42edbdfb6
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0da672fc2c69d3d7fd4c524c2d873ca725586d97
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