try not zeroing registers in start_pipeline
Generally stages take care of state setup themselves, either with seed_shader, constant_color, a load, etc. I think these zeros may be unnecessarily cautious. This can't make anything draw more correctly, but it could make things - draw wrong - draw more slowly - draw more quickly so it's an interesting thing to try and keep an eye on. Change-Id: I7e5ea3cd79e55a65e1dbd214601e147ba3815b87 Reviewed-on: https://skia-review.googlesource.com/20976 Reviewed-by: Mike Reed <reed@google.com> Commit-Queue: Mike Klein <mtklein@chromium.org>
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -53,7 +53,11 @@ using Stage = void(K* k, void** program, size_t x, size_t y, size_t tail, F,F,F,
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#endif
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#endif
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MAYBE_MSABI
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MAYBE_MSABI
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extern "C" void WRAP(start_pipeline)(size_t x, size_t y, size_t limit, void** program, K* k) {
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extern "C" void WRAP(start_pipeline)(size_t x, size_t y, size_t limit, void** program, K* k) {
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#if defined(JUMPER)
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F v;
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#else
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F v{};
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F v{};
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#endif
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auto start = (Stage*)load_and_inc(program);
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auto start = (Stage*)load_and_inc(program);
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while (x + kStride <= limit) {
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while (x + kStride <= limit) {
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start(k,program,x,y,0, v,v,v,v, v,v,v,v);
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start(k,program,x,y,0, v,v,v,v, v,v,v,v);
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@ -71,7 +71,11 @@ using Stage = void(K* k, void** program, size_t x, size_t y, size_t tail, F,F,F,
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#endif
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#endif
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MAYBE_MSABI
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MAYBE_MSABI
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extern "C" size_t WRAP(start_pipeline)(size_t x, size_t y, size_t limit, void** program, K* k) {
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extern "C" size_t WRAP(start_pipeline)(size_t x, size_t y, size_t limit, void** program, K* k) {
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#if defined(JUMPER)
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F v;
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#else
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F v{};
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F v{};
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#endif
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auto start = (Stage*)load_and_inc(program);
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auto start = (Stage*)load_and_inc(program);
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while (x + kStride <= limit) {
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while (x + kStride <= limit) {
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start(k,program,x,y,0, v,v,v,v, v,v,v,v);
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start(k,program,x,y,0, v,v,v,v, v,v,v,v);
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