vbroadcastss
This shows off a little how easy backwards-only labels are. The rip == rbp + Mod::Indirect convention isn't something you'd be able to guess without just looking at the docs. I'm not actually sure if you can only use rbp or also r13, but LLVM seems to always do the equivalent of rbp... might just be that high bit in VEX is ignored: they're registers 5 and 13, 8 apart, only distinguished by that bit. Convenienly RIP addressing is always 32-bit, so there's no benefit to spending time checking whether the offset fits in a byte, though most of our offsets would. Change-Id: I01b7fb1500667e1bf98490d5144459f92e1b375d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222857 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
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@ -477,14 +477,14 @@ namespace skvm {
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uint8_t bytes[3];
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};
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static VEX vex(bool WE, // Like REX W for int operations, or opcode extension for float?
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bool R, // Same as REX R. Pass high bit of dst register, dst>>3.
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bool X, // Same as REX X.
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bool B, // Same as REX B. Pass high bit of y register, y>>3.
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int map, // SSE opcode map selector: 0x0f, 0x380f, 0x3a0f.
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int x, // 4-bit second operand register, our x, called vvvv in docs.
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bool L, // Set for 256-bit ymm operations, off for 128-bit xmm.
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int pp) { // SSE mandatory prefix: 0x66, 0xf3, 0xf2, else none.
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static VEX vex(bool WE, // Like REX W for int operations, or opcode extension for float?
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bool R, // Same as REX R. Pass high bit of dst register, dst>>3.
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bool X, // Same as REX X.
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bool B, // Same as REX B. Pass y>>3 for 3-arg ops, x>>3 for 2-arg.
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int map, // SSE opcode map selector: 0x0f, 0x380f, 0x3a0f.
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int vvvv, // 4-bit second operand register. Pass our x for 3-arg ops.
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bool L, // Set for 256-bit ymm operations, off for 128-bit xmm.
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int pp) { // SSE mandatory prefix: 0x66, 0xf3, 0xf2, else none.
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// Pack x86 opcode map selector to 5-bit VEX encoding.
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map = [map]{
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@ -513,22 +513,22 @@ namespace skvm {
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// With these conditions met, we can optionally compress VEX to 2-byte.
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vex.len = 2;
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vex.bytes[0] = 0xc5;
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vex.bytes[1] = (pp & 3) << 0
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| (L & 1) << 2
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| (~x & 15) << 3
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| (~R & 1) << 7;
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vex.bytes[1] = (pp & 3) << 0
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| (L & 1) << 2
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| (~vvvv & 15) << 3
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| (~R & 1) << 7;
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} else {
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// We could use this 3-byte VEX prefix all the time if we like.
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vex.len = 3;
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vex.bytes[0] = 0xc4;
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vex.bytes[1] = (map & 31) << 0
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| (~B & 1) << 5
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| (~X & 1) << 6
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| (~R & 1) << 7;
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vex.bytes[2] = (pp & 3) << 0
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| (L & 1) << 2
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| (~x & 15) << 3
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| (WE & 1) << 7;
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vex.bytes[1] = (map & 31) << 0
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| (~B & 1) << 5
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| (~X & 1) << 6
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| (~R & 1) << 7;
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vex.bytes[2] = (pp & 3) << 0
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| (L & 1) << 2
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| (~vvvv & 15) << 3
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| (WE & 1) << 7;
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}
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return vex;
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}
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@ -642,6 +642,25 @@ namespace skvm {
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void Assembler::vcvtdq2ps (Ymm dst, Ymm x) { this->op(0, 0x0f,0x5b, dst,x); }
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void Assembler::vcvttps2dq(Ymm dst, Ymm x) { this->op(0xf3,0x0f,0x5b, dst,x); }
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Assembler::Label Assembler::here() {
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return { this->size() };
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}
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void Assembler::vbroadcastss(Ymm dst, Label l) {
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// IP-relative addressing uses Mod::Indirect with the R/M encoded as-if rbp or r13.
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int rip = rbp;
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VEX v = vex(0, dst>>3, 0, rip>>3,
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0x380f, 0, /*ymm?*/1, 0x66);
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this->byte(v.bytes, v.len);
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this->byte(0x18);
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this->byte(mod_rm(Mod::Indirect, dst&7, rip&7));
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// IP relative loads are relative to IP _after_ this instruction.
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int imm = l.offset - (here().offset + 4);
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this->byte(&imm, 4);
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}
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static bool can_jit(int regs, int nargs) {
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return true
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&& SkCpu::Supports(SkCpu::HSW) // TODO: SSE4.1 target?
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@ -736,7 +755,7 @@ namespace skvm {
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// Map from splat bit pattern to 4-byte aligned data location holding that pattern.
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// (If we were really brave we could just point at the copy we already have in Program...)
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std::unordered_map<int, Xbyak::Label> splats;
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std::unordered_map<int, A::Label> splats;
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for (const Program::Instruction& inst : instructions) {
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if (inst.op == Op::splat) {
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// Splats are deduplicated at an earlier layer, so we shouldn't find any duplicates.
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@ -748,7 +767,7 @@ namespace skvm {
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SkASSERT(splats.end() == splats.find(inst.y.imm));
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SkASSERT(a.size() % 4 == 0);
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Xbyak::Label label = X.L();
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A::Label label = a.here();
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a.byte(&inst.y.imm, 4);
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splats[inst.y.imm] = label;
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}
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@ -793,8 +812,7 @@ namespace skvm {
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case Op::load8: X.vpmovzxbd(r(d), X.ptr[xarg(y.imm)]); break;
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case Op::load32: X.vmovups (r(d), X.ptr[xarg(y.imm)]); break;
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case Op::splat: X.vbroadcastss(r(d), X.ptr[X.rip + splats[y.imm]]);
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break;
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case Op::splat: a.vbroadcastss(ar(d), splats[y.imm]); break;
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case Op::add_f32: a.vaddps(ar(d), ar(x), ar(y.id)); break;
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case Op::sub_f32: a.vsubps(ar(d), ar(x), ar(y.id)); break;
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@ -71,6 +71,11 @@ namespace skvm {
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using DstEqOpX = void(Ymm dst, Ymm x);
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DstEqOpX vcvtdq2ps, vcvttps2dq;
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struct Label { size_t offset; };
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Label here();
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void vbroadcastss(Ymm dst, Label);
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//private:
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std::unique_ptr<Xbyak::CodeGenerator> X;
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private:
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@ -290,6 +290,25 @@ DEF_TEST(SkVM_Assembler, r) {
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},{
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0xc4,0xe3,0xfd, 0x00,0xca, 0x05,
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});
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test_asm(r, [&](A& a) {
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A::Label l = a.here();
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a.byte(1);
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a.byte(2);
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a.byte(3);
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a.byte(4);
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a.vbroadcastss(A::ymm0 , l);
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a.vbroadcastss(A::ymm1 , l);
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a.vbroadcastss(A::ymm8 , l);
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a.vbroadcastss(A::ymm15, l);
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},{
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0x01, 0x02, 0x03, 0x4,
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/* VEX */ /*op*/ /* ModRM */ /* offset */
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0xc4, 0xe2, 0x7d, 0x18, 0b00'000'101, 0xf3,0xff,0xff,0xff, // 0xfffffff3 == -13
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0xc4, 0xe2, 0x7d, 0x18, 0b00'001'101, 0xea,0xff,0xff,0xff, // 0xffffffea == -22
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0xc4, 0x62, 0x7d, 0x18, 0b00'000'101, 0xe1,0xff,0xff,0xff, // 0xffffffe1 == -31
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0xc4, 0x62, 0x7d, 0x18, 0b00'111'101, 0xd8,0xff,0xff,0xff, // 0xffffffd8 == -40
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});
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}
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#endif
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