Add arm tail code.
CQ_INCLUDE_TRYBOTS=skia.primary:Test-Android-Clang-Nexus10-CPU-Exynos5250-arm-Release-Android Change-Id: Ia0e9f32d0324e66c9d4812dbb156a2b858d49a13 Reviewed-on: https://skia-review.googlesource.com/18127 Commit-Queue: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@chromium.org> Reviewed-by: Mike Klein <mtklein@chromium.org>
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@ -131,7 +131,7 @@ static SkJumper_Engine choose_engine() {
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return {
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#define M(stage) ASM(stage, vfp4),
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{ SK_RASTER_PIPELINE_STAGES(M) },
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2, M(start_pipeline) M(just_return)
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1, M(start_pipeline) M(just_return)
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#undef M
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};
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}
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File diff suppressed because it is too large
Load Diff
@ -76,7 +76,7 @@ struct LazyCtx {
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// We're finally going to get to what a Stage function looks like!
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// It's best to jump down to the #else case first, then to come back up here for AVX.
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#if defined(JUMPER) && defined(__SSE2__)
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#if defined(JUMPER) && (defined(__SSE2__) || defined(__arm__))
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// Process the tail on all x86 processors with SSE2 or better instructions.
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// tail == 0 ~~> work on a full kStride pixels
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// tail != 0 ~~> work on only the first tail pixels
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@ -182,7 +182,13 @@
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SI void load3(const uint16_t* ptr, size_t tail, U16* r, U16* g, U16* b) {
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uint16x4x3_t rgb;
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rgb = vld3_lane_u16(ptr + 0, rgb, 0);
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rgb = vld3_lane_u16(ptr + 3, rgb, 1);
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if (__builtin_expect(tail, 0)) {
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vset_lane_u16(0, rgb.val[0], 1);
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vset_lane_u16(0, rgb.val[1], 1);
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vset_lane_u16(0, rgb.val[2], 1);
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} else {
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rgb = vld3_lane_u16(ptr + 3, rgb, 1);
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}
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*r = unaligned_load<U16>(rgb.val+0);
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*g = unaligned_load<U16>(rgb.val+1);
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*b = unaligned_load<U16>(rgb.val+2);
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@ -190,7 +196,14 @@
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SI void load4(const uint16_t* ptr, size_t tail, U16* r, U16* g, U16* b, U16* a) {
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uint16x4x4_t rgba;
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rgba = vld4_lane_u16(ptr + 0, rgba, 0);
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rgba = vld4_lane_u16(ptr + 4, rgba, 1);
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if (__builtin_expect(tail, 0)) {
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vset_lane_u16(0, rgba.val[0], 1);
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vset_lane_u16(0, rgba.val[1], 1);
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vset_lane_u16(0, rgba.val[2], 1);
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vset_lane_u16(0, rgba.val[3], 1);
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} else {
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rgba = vld4_lane_u16(ptr + 4, rgba, 1);
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}
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*r = unaligned_load<U16>(rgba.val+0);
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*g = unaligned_load<U16>(rgba.val+1);
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*b = unaligned_load<U16>(rgba.val+2);
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@ -204,18 +217,29 @@
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widen_cast<uint16x4_t>(a),
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}};
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vst4_lane_u16(ptr + 0, rgba, 0);
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vst4_lane_u16(ptr + 4, rgba, 1);
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if (__builtin_expect(tail == 0, true)) {
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vst4_lane_u16(ptr + 4, rgba, 1);
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}
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}
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SI void load4(const float* ptr, size_t tail, F* r, F* g, F* b, F* a) {
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float32x2x4_t rgba = vld4_f32(ptr);
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float32x2x4_t rgba;
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if (__builtin_expect(tail, 0)) {
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rgba = vld4_dup_f32(ptr);
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} else {
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rgba = vld4_f32(ptr);
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}
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*r = rgba.val[0];
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*g = rgba.val[1];
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*b = rgba.val[2];
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*a = rgba.val[3];
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}
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SI void store4(float* ptr, size_t tail, F r, F g, F b, F a) {
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vst4_f32(ptr, (float32x2x4_t{{r,g,b,a}}));
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if (__builtin_expect(tail, 0)) {
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vst4_lane_f32(ptr, (float32x2x4_t{{r,g,b,a}}), 0);
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} else {
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vst4_f32(ptr, (float32x2x4_t{{r,g,b,a}}));
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}
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}
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@ -120,7 +120,7 @@ DEF_TEST(SkRasterPipeline_tail, r) {
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SkRasterPipeline_<256> p;
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p.append(SkRasterPipeline::load_f32, &src);
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p.append(SkRasterPipeline::store_f32, &dst);
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p.run(0, i % 4);
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p.run(0, i);
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for (unsigned j = 0; j < i; j++) {
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REPORTER_ASSERT(r,
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!memcmp(&data[j][0], &buffer[j][0], sizeof(buffer[j])));
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@ -149,7 +149,7 @@ DEF_TEST(SkRasterPipeline_tail, r) {
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SkRasterPipeline_<256> p;
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p.append(SkRasterPipeline::load_f16, &src);
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p.append(SkRasterPipeline::store_f16, &dst);
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p.run(0, i % 4);
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p.run(0, i);
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for (unsigned j = 0; j < i; j++) {
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REPORTER_ASSERT(r,
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!memcmp(&data[j][0], &buffer[j][0], sizeof(buffer[j])));
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@ -186,7 +186,7 @@ DEF_TEST(SkRasterPipeline_tail, r) {
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SkRasterPipeline_<256> p;
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p.append(SkRasterPipeline::load_rgb_u16_be, &src);
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p.append(SkRasterPipeline::store_f32, &dst);
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p.run(0, i % 4);
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p.run(0, i);
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for (unsigned j = 0; j < i; j++) {
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for (unsigned k = 0; k < 4; k++) {
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if (buffer[j][k] != answer[j][k]) {
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