b8310aefc4
This makes for a slightly more easier-to-read disassembly; register numbering no longer goes in reverse for vector assignment. Of course, it makes no difference in the actual execution. Change-Id: I86c5024bae1f73b1cd98252e4831207e47dc11eb Reviewed-on: https://skia-review.googlesource.com/c/skia/+/452323 Commit-Queue: Brian Osman <brianosman@google.com> Reviewed-by: Brian Osman <brianosman@google.com> Auto-Submit: John Stiles <johnstiles@google.com>
39 lines
925 B
Plaintext
39 lines
925 B
Plaintext
17 registers, 36 instructions:
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0 r0 = uniform32 ptr0 4
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1 r1 = uniform32 ptr0 8
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2 r2 = uniform32 ptr0 C
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3 r3 = uniform32 ptr0 10
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4 r4 = uniform32 ptr0 14
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5 r5 = uniform32 ptr0 18
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6 r6 = uniform32 ptr0 1C
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7 r7 = uniform32 ptr0 20
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8 r8 = splat 0 (0)
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9 r9 = splat FFFFFFFF (nan)
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10 r10 = trunc r1
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11 r8 = eq_i32 r8 r10
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12 r11 = bit_and r4 r8
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13 r12 = bit_and r5 r8
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14 r13 = bit_and r6 r8
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15 r14 = bit_and r7 r8
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16 r15 = bit_xor r9 r8
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17 r8 = bit_and r8 r15
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18 r16 = splat 1 (1.4012985e-45)
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19 r10 = eq_i32 r16 r10
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20 r10 = bit_or r8 r10
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21 r10 = bit_and r10 r15
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22 r11 = select r10 r0 r11
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23 r12 = select r10 r1 r12
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24 r13 = select r10 r2 r13
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25 r14 = select r10 r3 r14
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26 r10 = bit_xor r9 r10
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27 r10 = bit_and r15 r10
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28 r11 = select r10 r4 r11
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29 r12 = select r10 r5 r12
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30 r13 = select r10 r6 r13
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31 r14 = select r10 r7 r14
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loop:
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32 store32 ptr1 r11
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33 store32 ptr2 r12
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34 store32 ptr3 r13
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35 store32 ptr4 r14
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