ee40ec6dd6
pack(x,y,bits) as an alias for x|(y<<bits) only existed originally to
implement it with the SLI arm64 instruction, but I've since realized
that was misguided.
I had thought the assumption on pack ("(x & (y << bits)) == 0"), i.e.
"no overlap between x and the shifted y", was enough to make using SLI
legal, but it's actually not strong enough a requirement.
The SLI docs say "...inserts the result into the corresponding vector
element in the destination SIMD&FP register such that the new zero bits
created by the shift are not inserted but retain their existing value."
The key thing not mentioned there happens with zero bits _not_ created
by the shift, the ones already present at the top of y. They're of
course inserted, overwriting any previous values.
This means SLI (and so pack()) become strictly order dependent in a way
I had never intended. This will work as you'd think,
skvm::I32 px = splat(0);
px = pack(px, r, 0);
px = pack(px, a, 24);
but this version swapping the two calls to pack() will overwrite alpha,
skvm::I32 px = splat(0);
px = pack(px, a, 24);
px = pack(px, r, 0);
I find that error-prone, so I've removed Op::pack and replaced it
with a simple expansion to x|(y<<bits). That of course works in either
order.
This new test can't JIT at head, but if we implement the other missing
instructions (soon, dependent CL) it would start failing when JIT'd.
The interpreter and x86 were both fine, since they're both doing what's
now the only approach to pack(), the simple x|(y<<bits).
I've left assembler support for SLI in case we want to try it again.
Change-Id: Iaf879309d3e1d0a458a688f3a62556e55ab05e23
Reviewed-on: https://skia-review.googlesource.com/c/skia/+/337197
Reviewed-by: Herb Derby <herb@google.com>
Commit-Queue: Mike Klein <mtklein@google.com>
690 lines
16 KiB
Plaintext
690 lines
16 KiB
Plaintext
A8 over A8
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14 values (originally 17):
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↑ v0 = splat 437F0000 (255)
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↑ v1 = splat 3B808081 (0.0039215689)
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v2 = load8 arg(0)
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v3 = to_f32 v2
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v4 = mul_f32 v3 v1
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↑ v5 = splat 3F800000 (1)
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v6 = fnma_f32 v3 v1 v5
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v7 = load8 arg(1)
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v8 = to_f32 v7
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v9 = mul_f32 v8 v1
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v10 = fma_f32 v9 v6 v4
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v11 = mul_f32 v10 v0
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v12 = round v11
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store8 arg(1) v12
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6 registers, 14 instructions:
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0 r0 = splat 437F0000 (255)
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1 r1 = splat 3B808081 (0.0039215689)
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2 r2 = splat 3F800000 (1)
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loop:
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3 r3 = load8 arg(0)
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4 r3 = to_f32 r3
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5 r4 = mul_f32 r3 r1
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6 r3 = fnma_f32 r3 r1 r2
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7 r5 = load8 arg(1)
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8 r5 = to_f32 r5
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9 r5 = mul_f32 r5 r1
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10 r4 = fma_f32 r5 r3 r4
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11 r4 = mul_f32 r4 r0
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12 r4 = round r4
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13 store8 arg(1) r4
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A8 over G8
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19 values (originally 24):
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↑ v0 = splat 437F0000 (255)
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↑ v1 = splat 3D93DD98 (0.0722)
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↑ v2 = splat 3F800000 (1)
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↑ v3 = splat 3B808081 (0.0039215689)
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v4 = load8 arg(0)
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v5 = to_f32 v4
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v6 = fnma_f32 v5 v3 v2
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v7 = load8 arg(1)
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v8 = to_f32 v7
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v9 = mul_f32 v8 v3
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v10 = mul_f32 v9 v6
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v11 = mul_f32 v10 v1
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↑ v12 = splat 3F371759 (0.71520001)
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v13 = fma_f32 v10 v12 v11
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↑ v14 = splat 3E59B3D0 (0.21259999)
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v15 = fma_f32 v10 v14 v13
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v16 = mul_f32 v15 v0
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v17 = round v16
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store8 arg(1) v17
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8 registers, 19 instructions:
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0 r0 = splat 437F0000 (255)
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1 r1 = splat 3D93DD98 (0.0722)
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2 r2 = splat 3F800000 (1)
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3 r3 = splat 3B808081 (0.0039215689)
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4 r4 = splat 3F371759 (0.71520001)
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5 r5 = splat 3E59B3D0 (0.21259999)
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loop:
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6 r6 = load8 arg(0)
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7 r6 = to_f32 r6
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8 r6 = fnma_f32 r6 r3 r2
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9 r7 = load8 arg(1)
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10 r7 = to_f32 r7
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11 r7 = mul_f32 r7 r3
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12 r6 = mul_f32 r7 r6
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13 r7 = mul_f32 r6 r1
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14 r7 = fma_f32 r6 r4 r7
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15 r7 = fma_f32 r6 r5 r7
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16 r7 = mul_f32 r7 r0
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17 r7 = round r7
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18 store8 arg(1) r7
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A8 over RGBA_8888
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42 values (originally 44):
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↑ v0 = splat 437F0000 (255)
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↑ v1 = splat 3B808081 (0.0039215689)
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v2 = load8 arg(0)
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v3 = to_f32 v2
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v4 = mul_f32 v3 v1
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↑ v5 = splat 3F800000 (1)
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v6 = fnma_f32 v3 v1 v5
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v7 = load32 arg(1)
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v8 = shr_i32 v7 24
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v9 = to_f32 v8
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v10 = mul_f32 v9 v1
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v11 = fma_f32 v10 v6 v4
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v12 = mul_f32 v11 v0
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v13 = round v12
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v14 = shl_i32 v13 8
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v15 = shr_i32 v7 16
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↑ v16 = splat FF (3.5733111e-43)
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v17 = bit_and v16 v15
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v18 = to_f32 v17
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v19 = mul_f32 v18 v1
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v20 = mul_f32 v19 v6
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v21 = mul_f32 v20 v0
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v22 = round v21
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v23 = bit_or v22 v14
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v24 = shl_i32 v23 16
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v25 = shr_i32 v7 8
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v26 = bit_and v16 v25
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v27 = to_f32 v26
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v28 = mul_f32 v27 v1
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v29 = mul_f32 v28 v6
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v30 = mul_f32 v29 v0
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v31 = round v30
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v32 = shl_i32 v31 8
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v33 = bit_and v16 v7
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v34 = to_f32 v33
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v35 = mul_f32 v34 v1
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v36 = mul_f32 v35 v6
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v37 = mul_f32 v36 v0
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v38 = round v37
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v39 = bit_or v38 v32
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v40 = bit_or v39 v24
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store32 arg(1) v40
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8 registers, 42 instructions:
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0 r0 = splat 437F0000 (255)
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1 r1 = splat 3B808081 (0.0039215689)
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2 r2 = splat 3F800000 (1)
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3 r3 = splat FF (3.5733111e-43)
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loop:
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4 r4 = load8 arg(0)
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5 r4 = to_f32 r4
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6 r5 = mul_f32 r4 r1
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7 r4 = fnma_f32 r4 r1 r2
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8 r6 = load32 arg(1)
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9 r7 = shr_i32 r6 24
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10 r7 = to_f32 r7
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11 r7 = mul_f32 r7 r1
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12 r5 = fma_f32 r7 r4 r5
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13 r5 = mul_f32 r5 r0
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14 r5 = round r5
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15 r5 = shl_i32 r5 8
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16 r7 = shr_i32 r6 16
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17 r7 = bit_and r3 r7
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18 r7 = to_f32 r7
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19 r7 = mul_f32 r7 r1
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20 r7 = mul_f32 r7 r4
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21 r7 = mul_f32 r7 r0
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22 r7 = round r7
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23 r5 = bit_or r7 r5
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24 r5 = shl_i32 r5 16
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25 r7 = shr_i32 r6 8
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26 r7 = bit_and r3 r7
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27 r7 = to_f32 r7
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28 r7 = mul_f32 r7 r1
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29 r7 = mul_f32 r7 r4
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30 r7 = mul_f32 r7 r0
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31 r7 = round r7
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32 r7 = shl_i32 r7 8
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33 r6 = bit_and r3 r6
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34 r6 = to_f32 r6
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35 r6 = mul_f32 r6 r1
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36 r4 = mul_f32 r6 r4
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37 r4 = mul_f32 r4 r0
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38 r4 = round r4
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39 r7 = bit_or r4 r7
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40 r5 = bit_or r7 r5
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41 store32 arg(1) r5
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G8 over A8
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11 values (originally 15):
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↑ v0 = splat 437F0000 (255)
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↑ v1 = splat 3F800000 (1)
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↑ v2 = splat 0 (0)
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↑ v3 = splat 3B808081 (0.0039215689)
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v4 = load8 arg(1)
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v5 = to_f32 v4
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v6 = mul_f32 v5 v3
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v7 = fma_f32 v6 v2 v1
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v8 = mul_f32 v7 v0
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v9 = round v8
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store8 arg(1) v9
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5 registers, 11 instructions:
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0 r0 = splat 437F0000 (255)
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1 r1 = splat 3F800000 (1)
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2 r2 = splat 0 (0)
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3 r3 = splat 3B808081 (0.0039215689)
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loop:
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4 r4 = load8 arg(1)
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5 r4 = to_f32 r4
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6 r4 = mul_f32 r4 r3
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7 r4 = fma_f32 r4 r2 r1
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8 r4 = mul_f32 r4 r0
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9 r4 = round r4
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10 store8 arg(1) r4
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G8 over G8
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19 values (originally 23):
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↑ v0 = splat 437F0000 (255)
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↑ v1 = splat 3D93DD98 (0.0722)
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↑ v2 = splat 3B808081 (0.0039215689)
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v3 = load8 arg(0)
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v4 = to_f32 v3
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v5 = mul_f32 v4 v2
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↑ v6 = splat 0 (0)
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v7 = load8 arg(1)
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v8 = to_f32 v7
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v9 = mul_f32 v8 v2
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v10 = fma_f32 v9 v6 v5
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v11 = mul_f32 v10 v1
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↑ v12 = splat 3F371759 (0.71520001)
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v13 = fma_f32 v10 v12 v11
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↑ v14 = splat 3E59B3D0 (0.21259999)
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v15 = fma_f32 v10 v14 v13
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v16 = mul_f32 v15 v0
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v17 = round v16
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store8 arg(1) v17
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8 registers, 19 instructions:
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0 r0 = splat 437F0000 (255)
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1 r1 = splat 3D93DD98 (0.0722)
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2 r2 = splat 3B808081 (0.0039215689)
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3 r3 = splat 0 (0)
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4 r4 = splat 3F371759 (0.71520001)
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5 r5 = splat 3E59B3D0 (0.21259999)
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loop:
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6 r6 = load8 arg(0)
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7 r6 = to_f32 r6
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8 r6 = mul_f32 r6 r2
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9 r7 = load8 arg(1)
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10 r7 = to_f32 r7
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11 r7 = mul_f32 r7 r2
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12 r6 = fma_f32 r7 r3 r6
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13 r7 = mul_f32 r6 r1
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14 r7 = fma_f32 r6 r4 r7
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15 r7 = fma_f32 r6 r5 r7
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16 r7 = mul_f32 r7 r0
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17 r7 = round r7
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18 store8 arg(1) r7
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G8 over RGBA_8888
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42 values (originally 46):
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↑ v0 = splat 437F0000 (255)
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↑ v1 = splat 3F800000 (1)
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↑ v2 = splat 0 (0)
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↑ v3 = splat 3B808081 (0.0039215689)
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v4 = load32 arg(1)
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v5 = shr_i32 v4 24
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v6 = to_f32 v5
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v7 = mul_f32 v6 v3
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v8 = fma_f32 v7 v2 v1
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v9 = mul_f32 v8 v0
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v10 = round v9
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v11 = shl_i32 v10 8
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v12 = load8 arg(0)
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v13 = to_f32 v12
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v14 = mul_f32 v13 v3
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v15 = shr_i32 v4 16
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↑ v16 = splat FF (3.5733111e-43)
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v17 = bit_and v16 v15
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v18 = to_f32 v17
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v19 = mul_f32 v18 v3
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v20 = fma_f32 v19 v2 v14
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v21 = mul_f32 v20 v0
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v22 = round v21
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v23 = bit_or v22 v11
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v24 = shl_i32 v23 16
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v25 = shr_i32 v4 8
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v26 = bit_and v16 v25
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v27 = to_f32 v26
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v28 = mul_f32 v27 v3
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v29 = fma_f32 v28 v2 v14
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v30 = mul_f32 v29 v0
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v31 = round v30
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v32 = shl_i32 v31 8
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v33 = bit_and v16 v4
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v34 = to_f32 v33
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v35 = mul_f32 v34 v3
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v36 = fma_f32 v35 v2 v14
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v37 = mul_f32 v36 v0
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v38 = round v37
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v39 = bit_or v38 v32
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v40 = bit_or v39 v24
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store32 arg(1) v40
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9 registers, 42 instructions:
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0 r0 = splat 437F0000 (255)
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1 r1 = splat 3F800000 (1)
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2 r2 = splat 0 (0)
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3 r3 = splat 3B808081 (0.0039215689)
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4 r4 = splat FF (3.5733111e-43)
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loop:
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5 r5 = load32 arg(1)
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6 r6 = shr_i32 r5 24
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7 r6 = to_f32 r6
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8 r6 = mul_f32 r6 r3
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9 r6 = fma_f32 r6 r2 r1
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10 r6 = mul_f32 r6 r0
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11 r6 = round r6
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12 r6 = shl_i32 r6 8
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13 r7 = load8 arg(0)
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14 r7 = to_f32 r7
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15 r7 = mul_f32 r7 r3
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16 r8 = shr_i32 r5 16
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17 r8 = bit_and r4 r8
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18 r8 = to_f32 r8
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19 r8 = mul_f32 r8 r3
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20 r8 = fma_f32 r8 r2 r7
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21 r8 = mul_f32 r8 r0
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22 r8 = round r8
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23 r6 = bit_or r8 r6
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24 r6 = shl_i32 r6 16
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25 r8 = shr_i32 r5 8
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26 r8 = bit_and r4 r8
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27 r8 = to_f32 r8
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28 r8 = mul_f32 r8 r3
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29 r8 = fma_f32 r8 r2 r7
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30 r8 = mul_f32 r8 r0
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31 r8 = round r8
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32 r8 = shl_i32 r8 8
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33 r5 = bit_and r4 r5
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34 r5 = to_f32 r5
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35 r5 = mul_f32 r5 r3
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36 r7 = fma_f32 r5 r2 r7
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37 r7 = mul_f32 r7 r0
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38 r7 = round r7
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39 r8 = bit_or r7 r8
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40 r6 = bit_or r8 r6
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41 store32 arg(1) r6
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RGBA_8888 over A8
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15 values (originally 33):
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↑ v0 = splat 437F0000 (255)
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↑ v1 = splat 3B808081 (0.0039215689)
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v2 = load32 arg(0)
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v3 = shr_i32 v2 24
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v4 = to_f32 v3
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v5 = mul_f32 v4 v1
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↑ v6 = splat 3F800000 (1)
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v7 = fnma_f32 v4 v1 v6
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v8 = load8 arg(1)
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v9 = to_f32 v8
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v10 = mul_f32 v9 v1
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v11 = fma_f32 v10 v7 v5
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v12 = mul_f32 v11 v0
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v13 = round v12
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store8 arg(1) v13
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6 registers, 15 instructions:
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0 r0 = splat 437F0000 (255)
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1 r1 = splat 3B808081 (0.0039215689)
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2 r2 = splat 3F800000 (1)
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loop:
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3 r3 = load32 arg(0)
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4 r3 = shr_i32 r3 24
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5 r3 = to_f32 r3
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6 r4 = mul_f32 r3 r1
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7 r3 = fnma_f32 r3 r1 r2
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8 r5 = load8 arg(1)
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9 r5 = to_f32 r5
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10 r5 = mul_f32 r5 r1
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11 r4 = fma_f32 r5 r3 r4
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12 r4 = mul_f32 r4 r0
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13 r4 = round r4
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14 store8 arg(1) r4
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RGBA_8888 over G8
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34 values (originally 39):
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↑ v0 = splat 437F0000 (255)
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↑ v1 = splat 3D93DD98 (0.0722)
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↑ v2 = splat 3B808081 (0.0039215689)
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v3 = load32 arg(0)
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v4 = shr_i32 v3 16
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↑ v5 = splat FF (3.5733111e-43)
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v6 = bit_and v5 v4
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v7 = to_f32 v6
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v8 = mul_f32 v7 v2
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↑ v9 = splat 3F800000 (1)
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v10 = shr_i32 v3 24
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v11 = to_f32 v10
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v12 = fnma_f32 v11 v2 v9
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v13 = load8 arg(1)
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v14 = to_f32 v13
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v15 = mul_f32 v14 v2
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v16 = fma_f32 v15 v12 v8
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v17 = mul_f32 v16 v1
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↑ v18 = splat 3F371759 (0.71520001)
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v19 = shr_i32 v3 8
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v20 = bit_and v5 v19
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v21 = to_f32 v20
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v22 = mul_f32 v21 v2
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v23 = fma_f32 v15 v12 v22
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v24 = fma_f32 v23 v18 v17
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↑ v25 = splat 3E59B3D0 (0.21259999)
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v26 = bit_and v5 v3
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v27 = to_f32 v26
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v28 = mul_f32 v27 v2
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v29 = fma_f32 v15 v12 v28
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v30 = fma_f32 v29 v25 v24
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v31 = mul_f32 v30 v0
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v32 = round v31
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store8 arg(1) v32
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12 registers, 34 instructions:
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0 r0 = splat 437F0000 (255)
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1 r1 = splat 3D93DD98 (0.0722)
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2 r2 = splat 3B808081 (0.0039215689)
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3 r3 = splat FF (3.5733111e-43)
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|
4 r4 = splat 3F800000 (1)
|
|
5 r5 = splat 3F371759 (0.71520001)
|
|
6 r6 = splat 3E59B3D0 (0.21259999)
|
|
loop:
|
|
7 r7 = load32 arg(0)
|
|
8 r8 = shr_i32 r7 16
|
|
9 r8 = bit_and r3 r8
|
|
10 r8 = to_f32 r8
|
|
11 r8 = mul_f32 r8 r2
|
|
12 r9 = shr_i32 r7 24
|
|
13 r9 = to_f32 r9
|
|
14 r9 = fnma_f32 r9 r2 r4
|
|
15 r10 = load8 arg(1)
|
|
16 r10 = to_f32 r10
|
|
17 r10 = mul_f32 r10 r2
|
|
18 r8 = fma_f32 r10 r9 r8
|
|
19 r8 = mul_f32 r8 r1
|
|
20 r11 = shr_i32 r7 8
|
|
21 r11 = bit_and r3 r11
|
|
22 r11 = to_f32 r11
|
|
23 r11 = mul_f32 r11 r2
|
|
24 r11 = fma_f32 r10 r9 r11
|
|
25 r8 = fma_f32 r11 r5 r8
|
|
26 r7 = bit_and r3 r7
|
|
27 r7 = to_f32 r7
|
|
28 r7 = mul_f32 r7 r2
|
|
29 r7 = fma_f32 r10 r9 r7
|
|
30 r8 = fma_f32 r7 r6 r8
|
|
31 r8 = mul_f32 r8 r0
|
|
32 r8 = round r8
|
|
33 store8 arg(1) r8
|
|
|
|
RGBA_8888 over RGBA_8888
|
|
54 values (originally 58):
|
|
↑ v0 = splat 437F0000 (255)
|
|
↑ v1 = splat 3B808081 (0.0039215689)
|
|
v2 = load32 arg(0)
|
|
v3 = shr_i32 v2 24
|
|
v4 = to_f32 v3
|
|
v5 = mul_f32 v4 v1
|
|
↑ v6 = splat 3F800000 (1)
|
|
v7 = fnma_f32 v4 v1 v6
|
|
v8 = load32 arg(1)
|
|
v9 = shr_i32 v8 24
|
|
v10 = to_f32 v9
|
|
v11 = mul_f32 v10 v1
|
|
v12 = fma_f32 v11 v7 v5
|
|
v13 = mul_f32 v12 v0
|
|
v14 = round v13
|
|
v15 = shl_i32 v14 8
|
|
v16 = shr_i32 v2 16
|
|
↑ v17 = splat FF (3.5733111e-43)
|
|
v18 = bit_and v17 v16
|
|
v19 = to_f32 v18
|
|
v20 = mul_f32 v19 v1
|
|
v21 = shr_i32 v8 16
|
|
v22 = bit_and v17 v21
|
|
v23 = to_f32 v22
|
|
v24 = mul_f32 v23 v1
|
|
v25 = fma_f32 v24 v7 v20
|
|
v26 = mul_f32 v25 v0
|
|
v27 = round v26
|
|
v28 = bit_or v27 v15
|
|
v29 = shl_i32 v28 16
|
|
v30 = shr_i32 v2 8
|
|
v31 = bit_and v17 v30
|
|
v32 = to_f32 v31
|
|
v33 = mul_f32 v32 v1
|
|
v34 = shr_i32 v8 8
|
|
v35 = bit_and v17 v34
|
|
v36 = to_f32 v35
|
|
v37 = mul_f32 v36 v1
|
|
v38 = fma_f32 v37 v7 v33
|
|
v39 = mul_f32 v38 v0
|
|
v40 = round v39
|
|
v41 = shl_i32 v40 8
|
|
v42 = bit_and v17 v2
|
|
v43 = to_f32 v42
|
|
v44 = mul_f32 v43 v1
|
|
v45 = bit_and v17 v8
|
|
v46 = to_f32 v45
|
|
v47 = mul_f32 v46 v1
|
|
v48 = fma_f32 v47 v7 v44
|
|
v49 = mul_f32 v48 v0
|
|
v50 = round v49
|
|
v51 = bit_or v50 v41
|
|
v52 = bit_or v51 v29
|
|
store32 arg(1) v52
|
|
|
|
10 registers, 54 instructions:
|
|
0 r0 = splat 437F0000 (255)
|
|
1 r1 = splat 3B808081 (0.0039215689)
|
|
2 r2 = splat 3F800000 (1)
|
|
3 r3 = splat FF (3.5733111e-43)
|
|
loop:
|
|
4 r4 = load32 arg(0)
|
|
5 r5 = shr_i32 r4 24
|
|
6 r5 = to_f32 r5
|
|
7 r6 = mul_f32 r5 r1
|
|
8 r5 = fnma_f32 r5 r1 r2
|
|
9 r7 = load32 arg(1)
|
|
10 r8 = shr_i32 r7 24
|
|
11 r8 = to_f32 r8
|
|
12 r8 = mul_f32 r8 r1
|
|
13 r6 = fma_f32 r8 r5 r6
|
|
14 r6 = mul_f32 r6 r0
|
|
15 r6 = round r6
|
|
16 r6 = shl_i32 r6 8
|
|
17 r8 = shr_i32 r4 16
|
|
18 r8 = bit_and r3 r8
|
|
19 r8 = to_f32 r8
|
|
20 r8 = mul_f32 r8 r1
|
|
21 r9 = shr_i32 r7 16
|
|
22 r9 = bit_and r3 r9
|
|
23 r9 = to_f32 r9
|
|
24 r9 = mul_f32 r9 r1
|
|
25 r8 = fma_f32 r9 r5 r8
|
|
26 r8 = mul_f32 r8 r0
|
|
27 r8 = round r8
|
|
28 r6 = bit_or r8 r6
|
|
29 r6 = shl_i32 r6 16
|
|
30 r8 = shr_i32 r4 8
|
|
31 r8 = bit_and r3 r8
|
|
32 r8 = to_f32 r8
|
|
33 r8 = mul_f32 r8 r1
|
|
34 r9 = shr_i32 r7 8
|
|
35 r9 = bit_and r3 r9
|
|
36 r9 = to_f32 r9
|
|
37 r9 = mul_f32 r9 r1
|
|
38 r8 = fma_f32 r9 r5 r8
|
|
39 r8 = mul_f32 r8 r0
|
|
40 r8 = round r8
|
|
41 r8 = shl_i32 r8 8
|
|
42 r4 = bit_and r3 r4
|
|
43 r4 = to_f32 r4
|
|
44 r4 = mul_f32 r4 r1
|
|
45 r7 = bit_and r3 r7
|
|
46 r7 = to_f32 r7
|
|
47 r7 = mul_f32 r7 r1
|
|
48 r4 = fma_f32 r7 r5 r4
|
|
49 r4 = mul_f32 r4 r0
|
|
50 r4 = round r4
|
|
51 r8 = bit_or r4 r8
|
|
52 r6 = bit_or r8 r6
|
|
53 store32 arg(1) r6
|
|
|
|
I32 (Naive) 8888 over 8888
|
|
36 values (originally 36):
|
|
v0 = load32 arg(0)
|
|
v1 = shr_i32 v0 24
|
|
↑ v2 = splat 100 (3.5873241e-43)
|
|
v3 = sub_i32 v2 v1
|
|
v4 = load32 arg(1)
|
|
v5 = shr_i32 v4 24
|
|
v6 = mul_i32 v5 v3
|
|
v7 = shr_i32 v6 8
|
|
v8 = add_i32 v1 v7
|
|
v9 = shl_i32 v8 8
|
|
v10 = shr_i32 v4 16
|
|
↑ v11 = splat FF (3.5733111e-43)
|
|
v12 = bit_and v11 v10
|
|
v13 = mul_i32 v12 v3
|
|
v14 = shr_i32 v13 8
|
|
v15 = shr_i32 v0 16
|
|
v16 = bit_and v11 v15
|
|
v17 = add_i32 v16 v14
|
|
v18 = bit_or v17 v9
|
|
v19 = shl_i32 v18 16
|
|
v20 = shr_i32 v4 8
|
|
v21 = bit_and v11 v20
|
|
v22 = mul_i32 v21 v3
|
|
v23 = shr_i32 v22 8
|
|
v24 = shr_i32 v0 8
|
|
v25 = bit_and v11 v24
|
|
v26 = add_i32 v25 v23
|
|
v27 = shl_i32 v26 8
|
|
v28 = bit_and v11 v4
|
|
v29 = mul_i32 v28 v3
|
|
v30 = shr_i32 v29 8
|
|
v31 = bit_and v11 v0
|
|
v32 = add_i32 v31 v30
|
|
v33 = bit_or v32 v27
|
|
v34 = bit_or v33 v19
|
|
store32 arg(1) v34
|
|
|
|
8 registers, 36 instructions:
|
|
0 r0 = splat 100 (3.5873241e-43)
|
|
1 r1 = splat FF (3.5733111e-43)
|
|
loop:
|
|
2 r2 = load32 arg(0)
|
|
3 r3 = shr_i32 r2 24
|
|
4 r4 = sub_i32 r0 r3
|
|
5 r5 = load32 arg(1)
|
|
6 r6 = shr_i32 r5 24
|
|
7 r6 = mul_i32 r6 r4
|
|
8 r6 = shr_i32 r6 8
|
|
9 r6 = add_i32 r3 r6
|
|
10 r6 = shl_i32 r6 8
|
|
11 r3 = shr_i32 r5 16
|
|
12 r3 = bit_and r1 r3
|
|
13 r3 = mul_i32 r3 r4
|
|
14 r3 = shr_i32 r3 8
|
|
15 r7 = shr_i32 r2 16
|
|
16 r7 = bit_and r1 r7
|
|
17 r3 = add_i32 r7 r3
|
|
18 r6 = bit_or r3 r6
|
|
19 r6 = shl_i32 r6 16
|
|
20 r3 = shr_i32 r5 8
|
|
21 r3 = bit_and r1 r3
|
|
22 r3 = mul_i32 r3 r4
|
|
23 r3 = shr_i32 r3 8
|
|
24 r7 = shr_i32 r2 8
|
|
25 r7 = bit_and r1 r7
|
|
26 r3 = add_i32 r7 r3
|
|
27 r3 = shl_i32 r3 8
|
|
28 r5 = bit_and r1 r5
|
|
29 r4 = mul_i32 r5 r4
|
|
30 r4 = shr_i32 r4 8
|
|
31 r2 = bit_and r1 r2
|
|
32 r4 = add_i32 r2 r4
|
|
33 r3 = bit_or r4 r3
|
|
34 r6 = bit_or r3 r6
|
|
35 store32 arg(1) r6
|
|
|
|
26 values (originally 26):
|
|
v0 = load32 arg(1)
|
|
v1 = shr_i32 v0 24
|
|
v2 = load32 arg(0)
|
|
v3 = shr_i32 v2 24
|
|
v4 = add_i32 v3 v1
|
|
v5 = shl_i32 v4 8
|
|
v6 = shr_i32 v0 16
|
|
↑ v7 = splat FF (3.5733111e-43)
|
|
v8 = bit_and v7 v6
|
|
v9 = shr_i32 v2 16
|
|
v10 = bit_and v7 v9
|
|
v11 = add_i32 v10 v8
|
|
v12 = bit_or v11 v5
|
|
v13 = shl_i32 v12 16
|
|
v14 = shr_i32 v0 8
|
|
v15 = bit_and v7 v14
|
|
v16 = shr_i32 v2 8
|
|
v17 = bit_and v7 v16
|
|
v18 = add_i32 v17 v15
|
|
v19 = shl_i32 v18 8
|
|
v20 = bit_and v7 v0
|
|
v21 = bit_and v7 v2
|
|
v22 = add_i32 v21 v20
|
|
v23 = bit_or v22 v19
|
|
v24 = bit_or v23 v13
|
|
store32 arg(1) v24
|
|
|
|
6 registers, 26 instructions:
|
|
0 r0 = splat FF (3.5733111e-43)
|
|
loop:
|
|
1 r1 = load32 arg(1)
|
|
2 r2 = shr_i32 r1 24
|
|
3 r3 = load32 arg(0)
|
|
4 r4 = shr_i32 r3 24
|
|
5 r2 = add_i32 r4 r2
|
|
6 r2 = shl_i32 r2 8
|
|
7 r4 = shr_i32 r1 16
|
|
8 r4 = bit_and r0 r4
|
|
9 r5 = shr_i32 r3 16
|
|
10 r5 = bit_and r0 r5
|
|
11 r4 = add_i32 r5 r4
|
|
12 r2 = bit_or r4 r2
|
|
13 r2 = shl_i32 r2 16
|
|
14 r4 = shr_i32 r1 8
|
|
15 r4 = bit_and r0 r4
|
|
16 r5 = shr_i32 r3 8
|
|
17 r5 = bit_and r0 r5
|
|
18 r4 = add_i32 r5 r4
|
|
19 r4 = shl_i32 r4 8
|
|
20 r1 = bit_and r0 r1
|
|
21 r3 = bit_and r0 r3
|
|
22 r1 = add_i32 r3 r1
|
|
23 r4 = bit_or r1 r4
|
|
24 r2 = bit_or r4 r2
|
|
25 store32 arg(1) r2
|
|
|