d48488b5ea
Rewrite program instructions so that each value becomes available as
late as possible, just before it's used by another instruction. This
reorders blocks of instructions to reduce them number of temporary
registers in flight.
Take this example of the sort of program that we naturally write,
noting the registers needed as we progress down the right:
src = load32 ... (1)
sr = extract src ... (2)
sg = extract src ... (3)
sb = extract src ... (4)
sa = extract src ... (4, src dies)
dst = load32 ... (5)
dr = extract dst ... (6)
dg = extract dst ... (7)
db = extract dst ... (8)
da = extract dst ... (8, dst dies)
r = add sr dr (7, sr and dr die)
g = add sg dg (6, sg and dg die)
b = add sb db (5, sb and db die)
a = add sa da (4, sa and da die)
rg = pack r g ... (3, r and g die)
ba = pack b a ... (2, b and a die)
rgba = pack rg ba ... (1, rg and ba die)
store32 rgba ... (0, rgba dies)
That original ordering of the code needs 8 registers (perhaps with a
temporary 9th, but we'll ignore that here). This CL will rewrite the
program to something more like this by recursively issuing inputs only
once needed:
src = load32 ... (1)
sr = extract src ... (2)
dst = load32 ... (3)
dr = extract dst ... (4)
r = add sr dr (3, sr and dr die)
sg = extract src ... (4)
dg = extract dst ... (5)
g = add sg dg (4, sg and dg die)
rg = pack r g (3, r and g die)
sb = extract src ... (4)
db = extract dst ... (5)
b = add sb db (4, sb and db die)
sa = extract src ... (4, src dies)
da = extract dst ... (4, dst dies)
a = add sa da (3, sa and da die)
ba = pack b a (2, b and a die)
rgba = pack rg ba ... (1, rg and ba die)
store32 rgba ... (0)
That trims 3 registers off the example, just by reordering!
I've added the real version of this example to SkVMTest.cpp.
(Its 6th register comes from holding the 0xff byte mask used
by extract, in case you're curious).
I'll admit it's not exactly easy to work out how this reordering works
without a pen and paper or trial and error. I've tried to make the
implementation preserve the original program's order as much as makes
sense (i.e. when order is an otherwise arbitrary choice) to keep it
somewhat sane to follow.
This reordering naturally skips dead code, so pour one out for ☠️ .
We lose our cute dead code emoji marker, but on the other hand all code
downstream of Builder::done() can assume every instruction is live.
Change-Id: Iceffcd10fd7465eae51a39ef8eec7a7189766ba2
Reviewed-on: https://skia-review.googlesource.com/c/skia/+/249999
Commit-Queue: Mike Klein <mtklein@google.com>
Reviewed-by: Herb Derby <herb@google.com>
767 lines
16 KiB
Plaintext
767 lines
16 KiB
Plaintext
A8 over A8
|
|
15 values:
|
|
↑ v0 = splat 3B808081 (0.0039215689)
|
|
v1 = load8 arg(0)
|
|
v2 = to_f32 v1
|
|
v3 = mul_f32 v0 v2
|
|
v4 = load8 arg(1)
|
|
v5 = to_f32 v4
|
|
v6 = mul_f32 v0 v5
|
|
↑ v7 = splat 3F800000 (1)
|
|
v8 = sub_f32 v7 v3
|
|
v9 = mad_f32 v6 v8 v3
|
|
↑ v10 = splat 437F0000 (255)
|
|
↑ v11 = splat 3F000000 (0.5)
|
|
v12 = mad_f32 v9 v10 v11
|
|
v13 = to_i32 v12
|
|
store8 arg(1) v13
|
|
|
|
7 registers, 15 instructions:
|
|
r0 = splat 3B808081 (0.0039215689)
|
|
r1 = splat 3F800000 (1)
|
|
r2 = splat 437F0000 (255)
|
|
r3 = splat 3F000000 (0.5)
|
|
loop:
|
|
r4 = load8 arg(0)
|
|
r4 = to_f32 r4
|
|
r4 = mul_f32 r0 r4
|
|
r5 = load8 arg(1)
|
|
r5 = to_f32 r5
|
|
r5 = mul_f32 r0 r5
|
|
r6 = sub_f32 r1 r4
|
|
r4 = mad_f32 r5 r6 r4
|
|
r4 = mad_f32 r4 r2 r3
|
|
r4 = to_i32 r4
|
|
store8 arg(1) r4
|
|
|
|
A8 over G8
|
|
21 values:
|
|
↑ v0 = splat 3B808081 (0.0039215689)
|
|
v1 = load8 arg(1)
|
|
v2 = to_f32 v1
|
|
v3 = mul_f32 v0 v2
|
|
v4 = load8 arg(0)
|
|
v5 = to_f32 v4
|
|
v6 = mul_f32 v0 v5
|
|
↑ v7 = splat 3F800000 (1)
|
|
v8 = sub_f32 v7 v6
|
|
v9 = mul_f32 v3 v8
|
|
↑ v10 = splat 3E59B3D0 (0.21259999)
|
|
↑ v11 = splat 3F371759 (0.71520001)
|
|
↑ v12 = splat 3D93DD98 (0.0722)
|
|
v13 = mul_f32 v9 v12
|
|
v14 = mad_f32 v9 v11 v13
|
|
v15 = mad_f32 v9 v10 v14
|
|
↑ v16 = splat 437F0000 (255)
|
|
↑ v17 = splat 3F000000 (0.5)
|
|
v18 = mad_f32 v15 v16 v17
|
|
v19 = to_i32 v18
|
|
store8 arg(1) v19
|
|
|
|
9 registers, 21 instructions:
|
|
r0 = splat 3B808081 (0.0039215689)
|
|
r1 = splat 3F800000 (1)
|
|
r2 = splat 3E59B3D0 (0.21259999)
|
|
r3 = splat 3F371759 (0.71520001)
|
|
r4 = splat 3D93DD98 (0.0722)
|
|
r5 = splat 437F0000 (255)
|
|
r6 = splat 3F000000 (0.5)
|
|
loop:
|
|
r7 = load8 arg(1)
|
|
r7 = to_f32 r7
|
|
r7 = mul_f32 r0 r7
|
|
r8 = load8 arg(0)
|
|
r8 = to_f32 r8
|
|
r8 = mul_f32 r0 r8
|
|
r8 = sub_f32 r1 r8
|
|
r8 = mul_f32 r7 r8
|
|
r7 = mul_f32 r8 r4
|
|
r7 = mad_f32 r8 r3 r7
|
|
r7 = mad_f32 r8 r2 r7
|
|
r7 = mad_f32 r7 r5 r6
|
|
r7 = to_i32 r7
|
|
store8 arg(1) r7
|
|
|
|
A8 over RGBA_8888
|
|
38 values:
|
|
↑ v0 = splat 3B808081 (0.0039215689)
|
|
v1 = load32 arg(1)
|
|
↑ v2 = splat FF (3.5733111e-43)
|
|
v3 = extract v1 0 v2
|
|
v4 = to_f32 v3
|
|
v5 = mul_f32 v0 v4
|
|
v6 = load8 arg(0)
|
|
v7 = to_f32 v6
|
|
v8 = mul_f32 v0 v7
|
|
↑ v9 = splat 3F800000 (1)
|
|
v10 = sub_f32 v9 v8
|
|
v11 = mul_f32 v5 v10
|
|
↑ v12 = splat 437F0000 (255)
|
|
↑ v13 = splat 3F000000 (0.5)
|
|
v14 = mad_f32 v11 v12 v13
|
|
v15 = to_i32 v14
|
|
v16 = extract v1 8 v2
|
|
v17 = to_f32 v16
|
|
v18 = mul_f32 v0 v17
|
|
v19 = mul_f32 v18 v10
|
|
v20 = mad_f32 v19 v12 v13
|
|
v21 = to_i32 v20
|
|
v22 = pack v15 v21 8
|
|
v23 = extract v1 16 v2
|
|
v24 = to_f32 v23
|
|
v25 = mul_f32 v0 v24
|
|
v26 = mul_f32 v25 v10
|
|
v27 = mad_f32 v26 v12 v13
|
|
v28 = to_i32 v27
|
|
v29 = extract v1 24 v2
|
|
v30 = to_f32 v29
|
|
v31 = mul_f32 v0 v30
|
|
v32 = mad_f32 v31 v10 v8
|
|
v33 = mad_f32 v32 v12 v13
|
|
v34 = to_i32 v33
|
|
v35 = pack v28 v34 8
|
|
v36 = pack v22 v35 16
|
|
store32 arg(1) v36
|
|
|
|
10 registers, 38 instructions:
|
|
r0 = splat 3B808081 (0.0039215689)
|
|
r1 = splat FF (3.5733111e-43)
|
|
r2 = splat 3F800000 (1)
|
|
r3 = splat 437F0000 (255)
|
|
r4 = splat 3F000000 (0.5)
|
|
loop:
|
|
r5 = load32 arg(1)
|
|
r6 = extract r5 0 r1
|
|
r6 = to_f32 r6
|
|
r6 = mul_f32 r0 r6
|
|
r7 = load8 arg(0)
|
|
r7 = to_f32 r7
|
|
r7 = mul_f32 r0 r7
|
|
r8 = sub_f32 r2 r7
|
|
r6 = mul_f32 r6 r8
|
|
r6 = mad_f32 r6 r3 r4
|
|
r6 = to_i32 r6
|
|
r9 = extract r5 8 r1
|
|
r9 = to_f32 r9
|
|
r9 = mul_f32 r0 r9
|
|
r9 = mul_f32 r9 r8
|
|
r9 = mad_f32 r9 r3 r4
|
|
r9 = to_i32 r9
|
|
r9 = pack r6 r9 8
|
|
r6 = extract r5 16 r1
|
|
r6 = to_f32 r6
|
|
r6 = mul_f32 r0 r6
|
|
r6 = mul_f32 r6 r8
|
|
r6 = mad_f32 r6 r3 r4
|
|
r6 = to_i32 r6
|
|
r5 = extract r5 24 r1
|
|
r5 = to_f32 r5
|
|
r5 = mul_f32 r0 r5
|
|
r7 = mad_f32 r5 r8 r7
|
|
r7 = mad_f32 r7 r3 r4
|
|
r7 = to_i32 r7
|
|
r7 = pack r6 r7 8
|
|
r7 = pack r9 r7 16
|
|
store32 arg(1) r7
|
|
|
|
G8 over A8
|
|
12 values:
|
|
↑ v0 = splat 3F800000 (1)
|
|
↑ v1 = splat 3B808081 (0.0039215689)
|
|
v2 = load8 arg(1)
|
|
v3 = to_f32 v2
|
|
v4 = mul_f32 v1 v3
|
|
↑ v5 = sub_f32 v0 v0
|
|
v6 = mad_f32 v4 v5 v0
|
|
↑ v7 = splat 437F0000 (255)
|
|
↑ v8 = splat 3F000000 (0.5)
|
|
v9 = mad_f32 v6 v7 v8
|
|
v10 = to_i32 v9
|
|
store8 arg(1) v10
|
|
|
|
6 registers, 12 instructions:
|
|
r0 = splat 3F800000 (1)
|
|
r1 = splat 3B808081 (0.0039215689)
|
|
r2 = sub_f32 r0 r0
|
|
r3 = splat 437F0000 (255)
|
|
r4 = splat 3F000000 (0.5)
|
|
loop:
|
|
r5 = load8 arg(1)
|
|
r5 = to_f32 r5
|
|
r5 = mul_f32 r1 r5
|
|
r5 = mad_f32 r5 r2 r0
|
|
r5 = mad_f32 r5 r3 r4
|
|
r5 = to_i32 r5
|
|
store8 arg(1) r5
|
|
|
|
G8 over G8
|
|
21 values:
|
|
↑ v0 = splat 3B808081 (0.0039215689)
|
|
v1 = load8 arg(0)
|
|
v2 = to_f32 v1
|
|
v3 = mul_f32 v0 v2
|
|
v4 = load8 arg(1)
|
|
v5 = to_f32 v4
|
|
v6 = mul_f32 v0 v5
|
|
↟ v7 = splat 3F800000 (1)
|
|
↑ v8 = sub_f32 v7 v7
|
|
v9 = mad_f32 v6 v8 v3
|
|
↑ v10 = splat 3E59B3D0 (0.21259999)
|
|
↑ v11 = splat 3F371759 (0.71520001)
|
|
↑ v12 = splat 3D93DD98 (0.0722)
|
|
v13 = mul_f32 v9 v12
|
|
v14 = mad_f32 v9 v11 v13
|
|
v15 = mad_f32 v9 v10 v14
|
|
↑ v16 = splat 437F0000 (255)
|
|
↑ v17 = splat 3F000000 (0.5)
|
|
v18 = mad_f32 v15 v16 v17
|
|
v19 = to_i32 v18
|
|
store8 arg(1) v19
|
|
|
|
9 registers, 21 instructions:
|
|
r0 = splat 3B808081 (0.0039215689)
|
|
r1 = splat 3F800000 (1)
|
|
r1 = sub_f32 r1 r1
|
|
r2 = splat 3E59B3D0 (0.21259999)
|
|
r3 = splat 3F371759 (0.71520001)
|
|
r4 = splat 3D93DD98 (0.0722)
|
|
r5 = splat 437F0000 (255)
|
|
r6 = splat 3F000000 (0.5)
|
|
loop:
|
|
r7 = load8 arg(0)
|
|
r7 = to_f32 r7
|
|
r7 = mul_f32 r0 r7
|
|
r8 = load8 arg(1)
|
|
r8 = to_f32 r8
|
|
r8 = mul_f32 r0 r8
|
|
r7 = mad_f32 r8 r1 r7
|
|
r8 = mul_f32 r7 r4
|
|
r8 = mad_f32 r7 r3 r8
|
|
r8 = mad_f32 r7 r2 r8
|
|
r8 = mad_f32 r8 r5 r6
|
|
r8 = to_i32 r8
|
|
store8 arg(1) r8
|
|
|
|
G8 over RGBA_8888
|
|
38 values:
|
|
↑ v0 = splat 3B808081 (0.0039215689)
|
|
v1 = load8 arg(0)
|
|
v2 = to_f32 v1
|
|
v3 = mul_f32 v0 v2
|
|
v4 = load32 arg(1)
|
|
↑ v5 = splat FF (3.5733111e-43)
|
|
v6 = extract v4 0 v5
|
|
v7 = to_f32 v6
|
|
v8 = mul_f32 v0 v7
|
|
↑ v9 = splat 3F800000 (1)
|
|
↑ v10 = sub_f32 v9 v9
|
|
v11 = mad_f32 v8 v10 v3
|
|
↑ v12 = splat 437F0000 (255)
|
|
↑ v13 = splat 3F000000 (0.5)
|
|
v14 = mad_f32 v11 v12 v13
|
|
v15 = to_i32 v14
|
|
v16 = extract v4 8 v5
|
|
v17 = to_f32 v16
|
|
v18 = mul_f32 v0 v17
|
|
v19 = mad_f32 v18 v10 v3
|
|
v20 = mad_f32 v19 v12 v13
|
|
v21 = to_i32 v20
|
|
v22 = pack v15 v21 8
|
|
v23 = extract v4 16 v5
|
|
v24 = to_f32 v23
|
|
v25 = mul_f32 v0 v24
|
|
v26 = mad_f32 v25 v10 v3
|
|
v27 = mad_f32 v26 v12 v13
|
|
v28 = to_i32 v27
|
|
v29 = extract v4 24 v5
|
|
v30 = to_f32 v29
|
|
v31 = mul_f32 v0 v30
|
|
v32 = mad_f32 v31 v10 v9
|
|
v33 = mad_f32 v32 v12 v13
|
|
v34 = to_i32 v33
|
|
v35 = pack v28 v34 8
|
|
v36 = pack v22 v35 16
|
|
store32 arg(1) v36
|
|
|
|
10 registers, 38 instructions:
|
|
r0 = splat 3B808081 (0.0039215689)
|
|
r1 = splat FF (3.5733111e-43)
|
|
r2 = splat 3F800000 (1)
|
|
r3 = sub_f32 r2 r2
|
|
r4 = splat 437F0000 (255)
|
|
r5 = splat 3F000000 (0.5)
|
|
loop:
|
|
r6 = load8 arg(0)
|
|
r6 = to_f32 r6
|
|
r6 = mul_f32 r0 r6
|
|
r7 = load32 arg(1)
|
|
r8 = extract r7 0 r1
|
|
r8 = to_f32 r8
|
|
r8 = mul_f32 r0 r8
|
|
r8 = mad_f32 r8 r3 r6
|
|
r8 = mad_f32 r8 r4 r5
|
|
r8 = to_i32 r8
|
|
r9 = extract r7 8 r1
|
|
r9 = to_f32 r9
|
|
r9 = mul_f32 r0 r9
|
|
r9 = mad_f32 r9 r3 r6
|
|
r9 = mad_f32 r9 r4 r5
|
|
r9 = to_i32 r9
|
|
r9 = pack r8 r9 8
|
|
r8 = extract r7 16 r1
|
|
r8 = to_f32 r8
|
|
r8 = mul_f32 r0 r8
|
|
r6 = mad_f32 r8 r3 r6
|
|
r6 = mad_f32 r6 r4 r5
|
|
r6 = to_i32 r6
|
|
r7 = extract r7 24 r1
|
|
r7 = to_f32 r7
|
|
r7 = mul_f32 r0 r7
|
|
r7 = mad_f32 r7 r3 r2
|
|
r7 = mad_f32 r7 r4 r5
|
|
r7 = to_i32 r7
|
|
r7 = pack r6 r7 8
|
|
r7 = pack r9 r7 16
|
|
store32 arg(1) r7
|
|
|
|
RGBA_8888 over A8
|
|
17 values:
|
|
↑ v0 = splat 3B808081 (0.0039215689)
|
|
v1 = load32 arg(0)
|
|
↑ v2 = splat FF (3.5733111e-43)
|
|
v3 = extract v1 24 v2
|
|
v4 = to_f32 v3
|
|
v5 = mul_f32 v0 v4
|
|
v6 = load8 arg(1)
|
|
v7 = to_f32 v6
|
|
v8 = mul_f32 v0 v7
|
|
↑ v9 = splat 3F800000 (1)
|
|
v10 = sub_f32 v9 v5
|
|
v11 = mad_f32 v8 v10 v5
|
|
↑ v12 = splat 437F0000 (255)
|
|
↑ v13 = splat 3F000000 (0.5)
|
|
v14 = mad_f32 v11 v12 v13
|
|
v15 = to_i32 v14
|
|
store8 arg(1) v15
|
|
|
|
8 registers, 17 instructions:
|
|
r0 = splat 3B808081 (0.0039215689)
|
|
r1 = splat FF (3.5733111e-43)
|
|
r2 = splat 3F800000 (1)
|
|
r3 = splat 437F0000 (255)
|
|
r4 = splat 3F000000 (0.5)
|
|
loop:
|
|
r5 = load32 arg(0)
|
|
r5 = extract r5 24 r1
|
|
r5 = to_f32 r5
|
|
r5 = mul_f32 r0 r5
|
|
r6 = load8 arg(1)
|
|
r6 = to_f32 r6
|
|
r6 = mul_f32 r0 r6
|
|
r7 = sub_f32 r2 r5
|
|
r5 = mad_f32 r6 r7 r5
|
|
r5 = mad_f32 r5 r3 r4
|
|
r5 = to_i32 r5
|
|
store8 arg(1) r5
|
|
|
|
RGBA_8888 over G8
|
|
34 values:
|
|
↑ v0 = splat 3B808081 (0.0039215689)
|
|
v1 = load32 arg(0)
|
|
↑ v2 = splat FF (3.5733111e-43)
|
|
v3 = extract v1 0 v2
|
|
v4 = to_f32 v3
|
|
v5 = mul_f32 v0 v4
|
|
v6 = load8 arg(1)
|
|
v7 = to_f32 v6
|
|
v8 = mul_f32 v0 v7
|
|
v9 = extract v1 24 v2
|
|
v10 = to_f32 v9
|
|
v11 = mul_f32 v0 v10
|
|
↑ v12 = splat 3F800000 (1)
|
|
v13 = sub_f32 v12 v11
|
|
v14 = mad_f32 v8 v13 v5
|
|
↑ v15 = splat 3E59B3D0 (0.21259999)
|
|
v16 = extract v1 8 v2
|
|
v17 = to_f32 v16
|
|
v18 = mul_f32 v0 v17
|
|
v19 = mad_f32 v8 v13 v18
|
|
↑ v20 = splat 3F371759 (0.71520001)
|
|
v21 = extract v1 16 v2
|
|
v22 = to_f32 v21
|
|
v23 = mul_f32 v0 v22
|
|
v24 = mad_f32 v8 v13 v23
|
|
↑ v25 = splat 3D93DD98 (0.0722)
|
|
v26 = mul_f32 v24 v25
|
|
v27 = mad_f32 v19 v20 v26
|
|
v28 = mad_f32 v14 v15 v27
|
|
↑ v29 = splat 437F0000 (255)
|
|
↑ v30 = splat 3F000000 (0.5)
|
|
v31 = mad_f32 v28 v29 v30
|
|
v32 = to_i32 v31
|
|
store8 arg(1) v32
|
|
|
|
13 registers, 34 instructions:
|
|
r0 = splat 3B808081 (0.0039215689)
|
|
r1 = splat FF (3.5733111e-43)
|
|
r2 = splat 3F800000 (1)
|
|
r3 = splat 3E59B3D0 (0.21259999)
|
|
r4 = splat 3F371759 (0.71520001)
|
|
r5 = splat 3D93DD98 (0.0722)
|
|
r6 = splat 437F0000 (255)
|
|
r7 = splat 3F000000 (0.5)
|
|
loop:
|
|
r8 = load32 arg(0)
|
|
r9 = extract r8 0 r1
|
|
r9 = to_f32 r9
|
|
r9 = mul_f32 r0 r9
|
|
r10 = load8 arg(1)
|
|
r10 = to_f32 r10
|
|
r10 = mul_f32 r0 r10
|
|
r11 = extract r8 24 r1
|
|
r11 = to_f32 r11
|
|
r11 = mul_f32 r0 r11
|
|
r11 = sub_f32 r2 r11
|
|
r9 = mad_f32 r10 r11 r9
|
|
r12 = extract r8 8 r1
|
|
r12 = to_f32 r12
|
|
r12 = mul_f32 r0 r12
|
|
r12 = mad_f32 r10 r11 r12
|
|
r8 = extract r8 16 r1
|
|
r8 = to_f32 r8
|
|
r8 = mul_f32 r0 r8
|
|
r8 = mad_f32 r10 r11 r8
|
|
r8 = mul_f32 r8 r5
|
|
r8 = mad_f32 r12 r4 r8
|
|
r8 = mad_f32 r9 r3 r8
|
|
r8 = mad_f32 r8 r6 r7
|
|
r8 = to_i32 r8
|
|
store8 arg(1) r8
|
|
|
|
RGBA_8888 over RGBA_8888
|
|
48 values:
|
|
↑ v0 = splat 3B808081 (0.0039215689)
|
|
v1 = load32 arg(0)
|
|
↑ v2 = splat FF (3.5733111e-43)
|
|
v3 = extract v1 0 v2
|
|
v4 = to_f32 v3
|
|
v5 = mul_f32 v0 v4
|
|
v6 = load32 arg(1)
|
|
v7 = extract v6 0 v2
|
|
v8 = to_f32 v7
|
|
v9 = mul_f32 v0 v8
|
|
v10 = extract v1 24 v2
|
|
v11 = to_f32 v10
|
|
v12 = mul_f32 v0 v11
|
|
↑ v13 = splat 3F800000 (1)
|
|
v14 = sub_f32 v13 v12
|
|
v15 = mad_f32 v9 v14 v5
|
|
↑ v16 = splat 437F0000 (255)
|
|
↑ v17 = splat 3F000000 (0.5)
|
|
v18 = mad_f32 v15 v16 v17
|
|
v19 = to_i32 v18
|
|
v20 = extract v1 8 v2
|
|
v21 = to_f32 v20
|
|
v22 = mul_f32 v0 v21
|
|
v23 = extract v6 8 v2
|
|
v24 = to_f32 v23
|
|
v25 = mul_f32 v0 v24
|
|
v26 = mad_f32 v25 v14 v22
|
|
v27 = mad_f32 v26 v16 v17
|
|
v28 = to_i32 v27
|
|
v29 = pack v19 v28 8
|
|
v30 = extract v1 16 v2
|
|
v31 = to_f32 v30
|
|
v32 = mul_f32 v0 v31
|
|
v33 = extract v6 16 v2
|
|
v34 = to_f32 v33
|
|
v35 = mul_f32 v0 v34
|
|
v36 = mad_f32 v35 v14 v32
|
|
v37 = mad_f32 v36 v16 v17
|
|
v38 = to_i32 v37
|
|
v39 = extract v6 24 v2
|
|
v40 = to_f32 v39
|
|
v41 = mul_f32 v0 v40
|
|
v42 = mad_f32 v41 v14 v12
|
|
v43 = mad_f32 v42 v16 v17
|
|
v44 = to_i32 v43
|
|
v45 = pack v38 v44 8
|
|
v46 = pack v29 v45 16
|
|
store32 arg(1) v46
|
|
|
|
12 registers, 48 instructions:
|
|
r0 = splat 3B808081 (0.0039215689)
|
|
r1 = splat FF (3.5733111e-43)
|
|
r2 = splat 3F800000 (1)
|
|
r3 = splat 437F0000 (255)
|
|
r4 = splat 3F000000 (0.5)
|
|
loop:
|
|
r5 = load32 arg(0)
|
|
r6 = extract r5 0 r1
|
|
r6 = to_f32 r6
|
|
r6 = mul_f32 r0 r6
|
|
r7 = load32 arg(1)
|
|
r8 = extract r7 0 r1
|
|
r8 = to_f32 r8
|
|
r8 = mul_f32 r0 r8
|
|
r9 = extract r5 24 r1
|
|
r9 = to_f32 r9
|
|
r9 = mul_f32 r0 r9
|
|
r10 = sub_f32 r2 r9
|
|
r6 = mad_f32 r8 r10 r6
|
|
r6 = mad_f32 r6 r3 r4
|
|
r6 = to_i32 r6
|
|
r8 = extract r5 8 r1
|
|
r8 = to_f32 r8
|
|
r8 = mul_f32 r0 r8
|
|
r11 = extract r7 8 r1
|
|
r11 = to_f32 r11
|
|
r11 = mul_f32 r0 r11
|
|
r8 = mad_f32 r11 r10 r8
|
|
r8 = mad_f32 r8 r3 r4
|
|
r8 = to_i32 r8
|
|
r8 = pack r6 r8 8
|
|
r5 = extract r5 16 r1
|
|
r5 = to_f32 r5
|
|
r5 = mul_f32 r0 r5
|
|
r6 = extract r7 16 r1
|
|
r6 = to_f32 r6
|
|
r6 = mul_f32 r0 r6
|
|
r5 = mad_f32 r6 r10 r5
|
|
r5 = mad_f32 r5 r3 r4
|
|
r5 = to_i32 r5
|
|
r7 = extract r7 24 r1
|
|
r7 = to_f32 r7
|
|
r7 = mul_f32 r0 r7
|
|
r9 = mad_f32 r7 r10 r9
|
|
r9 = mad_f32 r9 r3 r4
|
|
r9 = to_i32 r9
|
|
r9 = pack r5 r9 8
|
|
r9 = pack r8 r9 16
|
|
store32 arg(1) r9
|
|
|
|
I32 (Naive) 8888 over 8888
|
|
29 values:
|
|
v0 = load32 arg(0)
|
|
↑ v1 = splat FF (3.5733111e-43)
|
|
v2 = extract v0 0 v1
|
|
v3 = load32 arg(1)
|
|
v4 = extract v3 0 v1
|
|
v5 = extract v0 24 v1
|
|
↑ v6 = splat 100 (3.5873241e-43)
|
|
v7 = sub_i32 v6 v5
|
|
v8 = mul_i32 v4 v7
|
|
v9 = shr_i32 v8 8
|
|
v10 = add_i32 v2 v9
|
|
v11 = extract v0 8 v1
|
|
v12 = extract v3 8 v1
|
|
v13 = mul_i32 v12 v7
|
|
v14 = shr_i32 v13 8
|
|
v15 = add_i32 v11 v14
|
|
v16 = pack v10 v15 8
|
|
v17 = extract v0 16 v1
|
|
v18 = extract v3 16 v1
|
|
v19 = mul_i32 v18 v7
|
|
v20 = shr_i32 v19 8
|
|
v21 = add_i32 v17 v20
|
|
v22 = extract v3 24 v1
|
|
v23 = mul_i32 v22 v7
|
|
v24 = shr_i32 v23 8
|
|
v25 = add_i32 v5 v24
|
|
v26 = pack v21 v25 8
|
|
v27 = pack v16 v26 16
|
|
store32 arg(1) v27
|
|
|
|
9 registers, 29 instructions:
|
|
r0 = splat FF (3.5733111e-43)
|
|
r1 = splat 100 (3.5873241e-43)
|
|
loop:
|
|
r2 = load32 arg(0)
|
|
r3 = extract r2 0 r0
|
|
r4 = load32 arg(1)
|
|
r5 = extract r4 0 r0
|
|
r6 = extract r2 24 r0
|
|
r7 = sub_i32 r1 r6
|
|
r5 = mul_i32 r5 r7
|
|
r5 = shr_i32 r5 8
|
|
r5 = add_i32 r3 r5
|
|
r3 = extract r2 8 r0
|
|
r8 = extract r4 8 r0
|
|
r8 = mul_i32 r8 r7
|
|
r8 = shr_i32 r8 8
|
|
r8 = add_i32 r3 r8
|
|
r8 = pack r5 r8 8
|
|
r2 = extract r2 16 r0
|
|
r5 = extract r4 16 r0
|
|
r5 = mul_i32 r5 r7
|
|
r5 = shr_i32 r5 8
|
|
r5 = add_i32 r2 r5
|
|
r4 = extract r4 24 r0
|
|
r7 = mul_i32 r4 r7
|
|
r7 = shr_i32 r7 8
|
|
r7 = add_i32 r6 r7
|
|
r7 = pack r5 r7 8
|
|
r7 = pack r8 r7 16
|
|
store32 arg(1) r7
|
|
|
|
I32 8888 over 8888
|
|
29 values:
|
|
v0 = load32 arg(0)
|
|
↑ v1 = splat FF (3.5733111e-43)
|
|
v2 = bit_and v0 v1
|
|
v3 = load32 arg(1)
|
|
v4 = bit_and v3 v1
|
|
v5 = shr_i32 v0 24
|
|
↑ v6 = splat 100 (3.5873241e-43)
|
|
v7 = sub_i32 v6 v5
|
|
v8 = mul_i16x2 v4 v7
|
|
v9 = shr_i32 v8 8
|
|
v10 = add_i32 v2 v9
|
|
v11 = bytes v0 2
|
|
v12 = bytes v3 2
|
|
v13 = mul_i16x2 v12 v7
|
|
v14 = shr_i32 v13 8
|
|
v15 = add_i32 v11 v14
|
|
v16 = pack v10 v15 8
|
|
v17 = bytes v0 3
|
|
v18 = bytes v3 3
|
|
v19 = mul_i16x2 v18 v7
|
|
v20 = shr_i32 v19 8
|
|
v21 = add_i32 v17 v20
|
|
v22 = shr_i32 v3 24
|
|
v23 = mul_i16x2 v22 v7
|
|
v24 = shr_i32 v23 8
|
|
v25 = add_i32 v5 v24
|
|
v26 = pack v21 v25 8
|
|
v27 = pack v16 v26 16
|
|
store32 arg(1) v27
|
|
|
|
9 registers, 29 instructions:
|
|
r0 = splat FF (3.5733111e-43)
|
|
r1 = splat 100 (3.5873241e-43)
|
|
loop:
|
|
r2 = load32 arg(0)
|
|
r3 = bit_and r2 r0
|
|
r4 = load32 arg(1)
|
|
r5 = bit_and r4 r0
|
|
r6 = shr_i32 r2 24
|
|
r7 = sub_i32 r1 r6
|
|
r5 = mul_i16x2 r5 r7
|
|
r5 = shr_i32 r5 8
|
|
r5 = add_i32 r3 r5
|
|
r3 = bytes r2 2
|
|
r8 = bytes r4 2
|
|
r8 = mul_i16x2 r8 r7
|
|
r8 = shr_i32 r8 8
|
|
r8 = add_i32 r3 r8
|
|
r8 = pack r5 r8 8
|
|
r2 = bytes r2 3
|
|
r5 = bytes r4 3
|
|
r5 = mul_i16x2 r5 r7
|
|
r5 = shr_i32 r5 8
|
|
r5 = add_i32 r2 r5
|
|
r4 = shr_i32 r4 24
|
|
r7 = mul_i16x2 r4 r7
|
|
r7 = shr_i32 r7 8
|
|
r7 = add_i32 r6 r7
|
|
r7 = pack r5 r7 8
|
|
r7 = pack r8 r7 16
|
|
store32 arg(1) r7
|
|
|
|
I32 (SWAR) 8888 over 8888
|
|
15 values:
|
|
v0 = load32 arg(0)
|
|
v1 = bytes v0 404
|
|
↑ v2 = splat 1000100 (2.3510604e-38)
|
|
v3 = sub_i16x2 v2 v1
|
|
v4 = load32 arg(1)
|
|
↑ v5 = splat FF00FF (2.3418409e-38)
|
|
v6 = bit_and v4 v5
|
|
v7 = mul_i16x2 v6 v3
|
|
v8 = shr_i16x2 v7 8
|
|
v9 = shr_i16x2 v4 8
|
|
v10 = mul_i16x2 v9 v3
|
|
v11 = bit_clear v10 v5
|
|
v12 = bit_or v8 v11
|
|
v13 = add_i32 v0 v12
|
|
store32 arg(1) v13
|
|
|
|
6 registers, 15 instructions:
|
|
r0 = splat 1000100 (2.3510604e-38)
|
|
r1 = splat FF00FF (2.3418409e-38)
|
|
loop:
|
|
r2 = load32 arg(0)
|
|
r3 = bytes r2 404
|
|
r3 = sub_i16x2 r0 r3
|
|
r4 = load32 arg(1)
|
|
r5 = bit_and r4 r1
|
|
r5 = mul_i16x2 r5 r3
|
|
r5 = shr_i16x2 r5 8
|
|
r4 = shr_i16x2 r4 8
|
|
r3 = mul_i16x2 r4 r3
|
|
r3 = bit_clear r3 r1
|
|
r3 = bit_or r5 r3
|
|
r3 = add_i32 r2 r3
|
|
store32 arg(1) r3
|
|
|
|
6 values:
|
|
↟ v0 = splat 1 (1.4012985e-45)
|
|
↟ v1 = splat 2 (2.8025969e-45)
|
|
↑ v2 = add_i32 v0 v1
|
|
v3 = load32 arg(0)
|
|
v4 = mul_i32 v3 v2
|
|
store32 arg(0) v4
|
|
|
|
2 registers, 6 instructions:
|
|
r0 = splat 1 (1.4012985e-45)
|
|
r1 = splat 2 (2.8025969e-45)
|
|
r1 = add_i32 r0 r1
|
|
loop:
|
|
r0 = load32 arg(0)
|
|
r0 = mul_i32 r0 r1
|
|
store32 arg(0) r0
|
|
|
|
19 values:
|
|
↑ v0 = splat FF (3.5733111e-43)
|
|
v1 = load32 arg(0)
|
|
v2 = extract v1 0 v0
|
|
v3 = load32 arg(1)
|
|
v4 = extract v3 0 v0
|
|
v5 = add_i32 v2 v4
|
|
v6 = extract v1 8 v0
|
|
v7 = extract v3 8 v0
|
|
v8 = add_i32 v6 v7
|
|
v9 = pack v5 v8 8
|
|
v10 = extract v1 16 v0
|
|
v11 = extract v3 16 v0
|
|
v12 = add_i32 v10 v11
|
|
v13 = extract v1 24 v0
|
|
v14 = extract v3 24 v0
|
|
v15 = add_i32 v13 v14
|
|
v16 = pack v12 v15 8
|
|
v17 = pack v9 v16 16
|
|
store32 arg(1) v17
|
|
|
|
6 registers, 19 instructions:
|
|
r0 = splat FF (3.5733111e-43)
|
|
loop:
|
|
r1 = load32 arg(0)
|
|
r2 = extract r1 0 r0
|
|
r3 = load32 arg(1)
|
|
r4 = extract r3 0 r0
|
|
r4 = add_i32 r2 r4
|
|
r2 = extract r1 8 r0
|
|
r5 = extract r3 8 r0
|
|
r5 = add_i32 r2 r5
|
|
r5 = pack r4 r5 8
|
|
r4 = extract r1 16 r0
|
|
r2 = extract r3 16 r0
|
|
r2 = add_i32 r4 r2
|
|
r1 = extract r1 24 r0
|
|
r3 = extract r3 24 r0
|
|
r3 = add_i32 r1 r3
|
|
r3 = pack r2 r3 8
|
|
r3 = pack r5 r3 16
|
|
store32 arg(1) r3
|
|
|