skia2/resources/SkVMTest.expected
Mike Klein f8db8a5516 disable fnma peephole
Change-Id: I66b251826211653586c64e8495cdfde7d7d8f1a2
Reviewed-on: https://skia-review.googlesource.com/c/skia/+/275410
Reviewed-by: Herb Derby <herb@google.com>
Reviewed-by: Mike Klein <mtklein@google.com>
2020-03-05 20:28:27 +00:00

799 lines
19 KiB
Plaintext

A8 over A8
15 values (originally 19):
↑ v0 = splat 3B808081 (0.0039215689)
v1 = load8 arg(0)
v2 = to_f32 v1
v3 = mul_f32 v2 v0
v4 = load8 arg(1)
v5 = to_f32 v4
v6 = mul_f32 v5 v0
↑ v7 = splat 3F800000 (1)
v8 = sub_f32 v7 v3
v9 = fma_f32 v6 v8 v3
↑ v10 = splat 437F0000 (255)
↑ v11 = splat 3F000000 (0.5)
v12 = fma_f32 v9 v10 v11
v13 = trunc v12
store8 arg(1) v13
7 registers, 15 instructions:
0 r0 = splat 3B808081 (0.0039215689)
1 r1 = splat 3F800000 (1)
2 r2 = splat 437F0000 (255)
3 r3 = splat 3F000000 (0.5)
loop:
4 r4 = load8 arg(0)
5 r4 = to_f32 r4
6 r4 = mul_f32 r4 r0
7 r5 = load8 arg(1)
8 r5 = to_f32 r5
9 r5 = mul_f32 r5 r0
10 r6 = sub_f32 r1 r4
11 r4 = fma_f32 r5 r6 r4
12 r4 = fma_f32 r4 r2 r3
13 r4 = trunc r4
14 store8 arg(1) r4
A8 over G8
21 values (originally 26):
↑ v0 = splat 3B808081 (0.0039215689)
v1 = load8 arg(1)
v2 = to_f32 v1
v3 = mul_f32 v2 v0
v4 = load8 arg(0)
v5 = to_f32 v4
v6 = mul_f32 v5 v0
↑ v7 = splat 3F800000 (1)
v8 = sub_f32 v7 v6
v9 = mul_f32 v3 v8
↑ v10 = splat 3E59B3D0 (0.21259999)
↑ v11 = splat 3F371759 (0.71520001)
↑ v12 = splat 3D93DD98 (0.0722)
v13 = mul_f32 v9 v12
v14 = fma_f32 v9 v11 v13
v15 = fma_f32 v9 v10 v14
↑ v16 = splat 437F0000 (255)
↑ v17 = splat 3F000000 (0.5)
v18 = fma_f32 v15 v16 v17
v19 = trunc v18
store8 arg(1) v19
9 registers, 21 instructions:
0 r0 = splat 3B808081 (0.0039215689)
1 r1 = splat 3F800000 (1)
2 r2 = splat 3E59B3D0 (0.21259999)
3 r3 = splat 3F371759 (0.71520001)
4 r4 = splat 3D93DD98 (0.0722)
5 r5 = splat 437F0000 (255)
6 r6 = splat 3F000000 (0.5)
loop:
7 r7 = load8 arg(1)
8 r7 = to_f32 r7
9 r7 = mul_f32 r7 r0
10 r8 = load8 arg(0)
11 r8 = to_f32 r8
12 r8 = mul_f32 r8 r0
13 r8 = sub_f32 r1 r8
14 r8 = mul_f32 r7 r8
15 r7 = mul_f32 r8 r4
16 r7 = fma_f32 r8 r3 r7
17 r7 = fma_f32 r8 r2 r7
18 r7 = fma_f32 r7 r5 r6
19 r7 = trunc r7
20 store8 arg(1) r7
A8 over RGBA_8888
40 values (originally 46):
↑ v0 = splat 3B808081 (0.0039215689)
v1 = load32 arg(1)
↑ v2 = splat FF (3.5733111e-43)
v3 = bit_and v2 v1
v4 = to_f32 v3
v5 = mul_f32 v4 v0
v6 = load8 arg(0)
v7 = to_f32 v6
v8 = mul_f32 v7 v0
↑ v9 = splat 3F800000 (1)
v10 = sub_f32 v9 v8
v11 = mul_f32 v5 v10
↑ v12 = splat 437F0000 (255)
↑ v13 = splat 3F000000 (0.5)
v14 = fma_f32 v11 v12 v13
v15 = trunc v14
v16 = shr_i32 v1 8
v17 = bit_and v2 v16
v18 = to_f32 v17
v19 = mul_f32 v18 v0
v20 = mul_f32 v19 v10
v21 = fma_f32 v20 v12 v13
v22 = trunc v21
v23 = pack v15 v22 8
v24 = shr_i32 v1 16
v25 = bit_and v2 v24
v26 = to_f32 v25
v27 = mul_f32 v26 v0
v28 = mul_f32 v27 v10
v29 = fma_f32 v28 v12 v13
v30 = trunc v29
v31 = shr_i32 v1 24
v32 = to_f32 v31
v33 = mul_f32 v32 v0
v34 = fma_f32 v33 v10 v8
v35 = fma_f32 v34 v12 v13
v36 = trunc v35
v37 = pack v30 v36 8
v38 = pack v23 v37 16
store32 arg(1) v38
10 registers, 40 instructions:
0 r0 = splat 3B808081 (0.0039215689)
1 r1 = splat FF (3.5733111e-43)
2 r2 = splat 3F800000 (1)
3 r3 = splat 437F0000 (255)
4 r4 = splat 3F000000 (0.5)
loop:
5 r5 = load32 arg(1)
6 r6 = bit_and r1 r5
7 r6 = to_f32 r6
8 r6 = mul_f32 r6 r0
9 r7 = load8 arg(0)
10 r7 = to_f32 r7
11 r7 = mul_f32 r7 r0
12 r8 = sub_f32 r2 r7
13 r6 = mul_f32 r6 r8
14 r6 = fma_f32 r6 r3 r4
15 r6 = trunc r6
16 r9 = shr_i32 r5 8
17 r9 = bit_and r1 r9
18 r9 = to_f32 r9
19 r9 = mul_f32 r9 r0
20 r9 = mul_f32 r9 r8
21 r9 = fma_f32 r9 r3 r4
22 r9 = trunc r9
23 r9 = pack r6 r9 8
24 r6 = shr_i32 r5 16
25 r6 = bit_and r1 r6
26 r6 = to_f32 r6
27 r6 = mul_f32 r6 r0
28 r6 = mul_f32 r6 r8
29 r6 = fma_f32 r6 r3 r4
30 r6 = trunc r6
31 r5 = shr_i32 r5 24
32 r5 = to_f32 r5
33 r5 = mul_f32 r5 r0
34 r7 = fma_f32 r5 r8 r7
35 r7 = fma_f32 r7 r3 r4
36 r7 = trunc r7
37 r7 = pack r6 r7 8
38 r7 = pack r9 r7 16
39 store32 arg(1) r7
G8 over A8
12 values (originally 17):
↑ v0 = splat 3F800000 (1)
↑ v1 = splat 0 (0)
↑ v2 = splat 3B808081 (0.0039215689)
v3 = load8 arg(1)
v4 = to_f32 v3
v5 = mul_f32 v4 v2
v6 = fma_f32 v5 v1 v0
↑ v7 = splat 437F0000 (255)
↑ v8 = splat 3F000000 (0.5)
v9 = fma_f32 v6 v7 v8
v10 = trunc v9
store8 arg(1) v10
6 registers, 12 instructions:
0 r0 = splat 3F800000 (1)
1 r1 = splat 0 (0)
2 r2 = splat 3B808081 (0.0039215689)
3 r3 = splat 437F0000 (255)
4 r4 = splat 3F000000 (0.5)
loop:
5 r5 = load8 arg(1)
6 r5 = to_f32 r5
7 r5 = mul_f32 r5 r2
8 r5 = fma_f32 r5 r1 r0
9 r5 = fma_f32 r5 r3 r4
10 r5 = trunc r5
11 store8 arg(1) r5
G8 over G8
20 values (originally 25):
↑ v0 = splat 3B808081 (0.0039215689)
v1 = load8 arg(0)
v2 = to_f32 v1
v3 = mul_f32 v2 v0
v4 = load8 arg(1)
v5 = to_f32 v4
v6 = mul_f32 v5 v0
↑ v7 = splat 0 (0)
v8 = fma_f32 v6 v7 v3
↑ v9 = splat 3E59B3D0 (0.21259999)
↑ v10 = splat 3F371759 (0.71520001)
↑ v11 = splat 3D93DD98 (0.0722)
v12 = mul_f32 v8 v11
v13 = fma_f32 v8 v10 v12
v14 = fma_f32 v8 v9 v13
↑ v15 = splat 437F0000 (255)
↑ v16 = splat 3F000000 (0.5)
v17 = fma_f32 v14 v15 v16
v18 = trunc v17
store8 arg(1) v18
9 registers, 20 instructions:
0 r0 = splat 3B808081 (0.0039215689)
1 r1 = splat 0 (0)
2 r2 = splat 3E59B3D0 (0.21259999)
3 r3 = splat 3F371759 (0.71520001)
4 r4 = splat 3D93DD98 (0.0722)
5 r5 = splat 437F0000 (255)
6 r6 = splat 3F000000 (0.5)
loop:
7 r7 = load8 arg(0)
8 r7 = to_f32 r7
9 r7 = mul_f32 r7 r0
10 r8 = load8 arg(1)
11 r8 = to_f32 r8
12 r8 = mul_f32 r8 r0
13 r7 = fma_f32 r8 r1 r7
14 r8 = mul_f32 r7 r4
15 r8 = fma_f32 r7 r3 r8
16 r8 = fma_f32 r7 r2 r8
17 r8 = fma_f32 r8 r5 r6
18 r8 = trunc r8
19 store8 arg(1) r8
G8 over RGBA_8888
40 values (originally 48):
↑ v0 = splat 3B808081 (0.0039215689)
v1 = load8 arg(0)
v2 = to_f32 v1
v3 = mul_f32 v2 v0
v4 = load32 arg(1)
↑ v5 = splat FF (3.5733111e-43)
v6 = bit_and v5 v4
v7 = to_f32 v6
v8 = mul_f32 v7 v0
↑ v9 = splat 0 (0)
v10 = fma_f32 v8 v9 v3
↑ v11 = splat 437F0000 (255)
↑ v12 = splat 3F000000 (0.5)
v13 = fma_f32 v10 v11 v12
v14 = trunc v13
v15 = shr_i32 v4 8
v16 = bit_and v5 v15
v17 = to_f32 v16
v18 = mul_f32 v17 v0
v19 = fma_f32 v18 v9 v3
v20 = fma_f32 v19 v11 v12
v21 = trunc v20
v22 = pack v14 v21 8
v23 = shr_i32 v4 16
v24 = bit_and v5 v23
v25 = to_f32 v24
v26 = mul_f32 v25 v0
v27 = fma_f32 v26 v9 v3
v28 = fma_f32 v27 v11 v12
v29 = trunc v28
↑ v30 = splat 3F800000 (1)
v31 = shr_i32 v4 24
v32 = to_f32 v31
v33 = mul_f32 v32 v0
v34 = fma_f32 v33 v9 v30
v35 = fma_f32 v34 v11 v12
v36 = trunc v35
v37 = pack v29 v36 8
v38 = pack v22 v37 16
store32 arg(1) v38
10 registers, 40 instructions:
0 r0 = splat 3B808081 (0.0039215689)
1 r1 = splat FF (3.5733111e-43)
2 r2 = splat 0 (0)
3 r3 = splat 437F0000 (255)
4 r4 = splat 3F000000 (0.5)
5 r5 = splat 3F800000 (1)
loop:
6 r6 = load8 arg(0)
7 r6 = to_f32 r6
8 r6 = mul_f32 r6 r0
9 r7 = load32 arg(1)
10 r8 = bit_and r1 r7
11 r8 = to_f32 r8
12 r8 = mul_f32 r8 r0
13 r8 = fma_f32 r8 r2 r6
14 r8 = fma_f32 r8 r3 r4
15 r8 = trunc r8
16 r9 = shr_i32 r7 8
17 r9 = bit_and r1 r9
18 r9 = to_f32 r9
19 r9 = mul_f32 r9 r0
20 r9 = fma_f32 r9 r2 r6
21 r9 = fma_f32 r9 r3 r4
22 r9 = trunc r9
23 r9 = pack r8 r9 8
24 r8 = shr_i32 r7 16
25 r8 = bit_and r1 r8
26 r8 = to_f32 r8
27 r8 = mul_f32 r8 r0
28 r6 = fma_f32 r8 r2 r6
29 r6 = fma_f32 r6 r3 r4
30 r6 = trunc r6
31 r7 = shr_i32 r7 24
32 r7 = to_f32 r7
33 r7 = mul_f32 r7 r0
34 r7 = fma_f32 r7 r2 r5
35 r7 = fma_f32 r7 r3 r4
36 r7 = trunc r7
37 r7 = pack r6 r7 8
38 r7 = pack r9 r7 16
39 store32 arg(1) r7
RGBA_8888 over A8
16 values (originally 35):
↑ v0 = splat 3B808081 (0.0039215689)
v1 = load32 arg(0)
v2 = shr_i32 v1 24
v3 = to_f32 v2
v4 = mul_f32 v3 v0
v5 = load8 arg(1)
v6 = to_f32 v5
v7 = mul_f32 v6 v0
↑ v8 = splat 3F800000 (1)
v9 = sub_f32 v8 v4
v10 = fma_f32 v7 v9 v4
↑ v11 = splat 437F0000 (255)
↑ v12 = splat 3F000000 (0.5)
v13 = fma_f32 v10 v11 v12
v14 = trunc v13
store8 arg(1) v14
7 registers, 16 instructions:
0 r0 = splat 3B808081 (0.0039215689)
1 r1 = splat 3F800000 (1)
2 r2 = splat 437F0000 (255)
3 r3 = splat 3F000000 (0.5)
loop:
4 r4 = load32 arg(0)
5 r4 = shr_i32 r4 24
6 r4 = to_f32 r4
7 r4 = mul_f32 r4 r0
8 r5 = load8 arg(1)
9 r5 = to_f32 r5
10 r5 = mul_f32 r5 r0
11 r6 = sub_f32 r1 r4
12 r4 = fma_f32 r5 r6 r4
13 r4 = fma_f32 r4 r2 r3
14 r4 = trunc r4
15 store8 arg(1) r4
RGBA_8888 over G8
36 values (originally 41):
↑ v0 = splat 3B808081 (0.0039215689)
v1 = load32 arg(0)
↑ v2 = splat FF (3.5733111e-43)
v3 = bit_and v2 v1
v4 = to_f32 v3
v5 = mul_f32 v4 v0
v6 = load8 arg(1)
v7 = to_f32 v6
v8 = mul_f32 v7 v0
v9 = shr_i32 v1 24
v10 = to_f32 v9
v11 = mul_f32 v10 v0
↑ v12 = splat 3F800000 (1)
v13 = sub_f32 v12 v11
v14 = fma_f32 v8 v13 v5
↑ v15 = splat 3E59B3D0 (0.21259999)
v16 = shr_i32 v1 8
v17 = bit_and v2 v16
v18 = to_f32 v17
v19 = mul_f32 v18 v0
v20 = fma_f32 v8 v13 v19
↑ v21 = splat 3F371759 (0.71520001)
v22 = shr_i32 v1 16
v23 = bit_and v2 v22
v24 = to_f32 v23
v25 = mul_f32 v24 v0
v26 = fma_f32 v8 v13 v25
↑ v27 = splat 3D93DD98 (0.0722)
v28 = mul_f32 v26 v27
v29 = fma_f32 v20 v21 v28
v30 = fma_f32 v14 v15 v29
↑ v31 = splat 437F0000 (255)
↑ v32 = splat 3F000000 (0.5)
v33 = fma_f32 v30 v31 v32
v34 = trunc v33
store8 arg(1) v34
13 registers, 36 instructions:
0 r0 = splat 3B808081 (0.0039215689)
1 r1 = splat FF (3.5733111e-43)
2 r2 = splat 3F800000 (1)
3 r3 = splat 3E59B3D0 (0.21259999)
4 r4 = splat 3F371759 (0.71520001)
5 r5 = splat 3D93DD98 (0.0722)
6 r6 = splat 437F0000 (255)
7 r7 = splat 3F000000 (0.5)
loop:
8 r8 = load32 arg(0)
9 r9 = bit_and r1 r8
10 r9 = to_f32 r9
11 r9 = mul_f32 r9 r0
12 r10 = load8 arg(1)
13 r10 = to_f32 r10
14 r10 = mul_f32 r10 r0
15 r11 = shr_i32 r8 24
16 r11 = to_f32 r11
17 r11 = mul_f32 r11 r0
18 r11 = sub_f32 r2 r11
19 r9 = fma_f32 r10 r11 r9
20 r12 = shr_i32 r8 8
21 r12 = bit_and r1 r12
22 r12 = to_f32 r12
23 r12 = mul_f32 r12 r0
24 r12 = fma_f32 r10 r11 r12
25 r8 = shr_i32 r8 16
26 r8 = bit_and r1 r8
27 r8 = to_f32 r8
28 r8 = mul_f32 r8 r0
29 r8 = fma_f32 r10 r11 r8
30 r8 = mul_f32 r8 r5
31 r8 = fma_f32 r12 r4 r8
32 r8 = fma_f32 r9 r3 r8
33 r8 = fma_f32 r8 r6 r7
34 r8 = trunc r8
35 store8 arg(1) r8
RGBA_8888 over RGBA_8888
52 values (originally 60):
↑ v0 = splat 3B808081 (0.0039215689)
v1 = load32 arg(0)
↑ v2 = splat FF (3.5733111e-43)
v3 = bit_and v2 v1
v4 = to_f32 v3
v5 = mul_f32 v4 v0
v6 = load32 arg(1)
v7 = bit_and v2 v6
v8 = to_f32 v7
v9 = mul_f32 v8 v0
v10 = shr_i32 v1 24
v11 = to_f32 v10
v12 = mul_f32 v11 v0
↑ v13 = splat 3F800000 (1)
v14 = sub_f32 v13 v12
v15 = fma_f32 v9 v14 v5
↑ v16 = splat 437F0000 (255)
↑ v17 = splat 3F000000 (0.5)
v18 = fma_f32 v15 v16 v17
v19 = trunc v18
v20 = shr_i32 v1 8
v21 = bit_and v2 v20
v22 = to_f32 v21
v23 = mul_f32 v22 v0
v24 = shr_i32 v6 8
v25 = bit_and v2 v24
v26 = to_f32 v25
v27 = mul_f32 v26 v0
v28 = fma_f32 v27 v14 v23
v29 = fma_f32 v28 v16 v17
v30 = trunc v29
v31 = pack v19 v30 8
v32 = shr_i32 v1 16
v33 = bit_and v2 v32
v34 = to_f32 v33
v35 = mul_f32 v34 v0
v36 = shr_i32 v6 16
v37 = bit_and v2 v36
v38 = to_f32 v37
v39 = mul_f32 v38 v0
v40 = fma_f32 v39 v14 v35
v41 = fma_f32 v40 v16 v17
v42 = trunc v41
v43 = shr_i32 v6 24
v44 = to_f32 v43
v45 = mul_f32 v44 v0
v46 = fma_f32 v45 v14 v12
v47 = fma_f32 v46 v16 v17
v48 = trunc v47
v49 = pack v42 v48 8
v50 = pack v31 v49 16
store32 arg(1) v50
12 registers, 52 instructions:
0 r0 = splat 3B808081 (0.0039215689)
1 r1 = splat FF (3.5733111e-43)
2 r2 = splat 3F800000 (1)
3 r3 = splat 437F0000 (255)
4 r4 = splat 3F000000 (0.5)
loop:
5 r5 = load32 arg(0)
6 r6 = bit_and r1 r5
7 r6 = to_f32 r6
8 r6 = mul_f32 r6 r0
9 r7 = load32 arg(1)
10 r8 = bit_and r1 r7
11 r8 = to_f32 r8
12 r8 = mul_f32 r8 r0
13 r9 = shr_i32 r5 24
14 r9 = to_f32 r9
15 r9 = mul_f32 r9 r0
16 r10 = sub_f32 r2 r9
17 r6 = fma_f32 r8 r10 r6
18 r6 = fma_f32 r6 r3 r4
19 r6 = trunc r6
20 r8 = shr_i32 r5 8
21 r8 = bit_and r1 r8
22 r8 = to_f32 r8
23 r8 = mul_f32 r8 r0
24 r11 = shr_i32 r7 8
25 r11 = bit_and r1 r11
26 r11 = to_f32 r11
27 r11 = mul_f32 r11 r0
28 r8 = fma_f32 r11 r10 r8
29 r8 = fma_f32 r8 r3 r4
30 r8 = trunc r8
31 r8 = pack r6 r8 8
32 r5 = shr_i32 r5 16
33 r5 = bit_and r1 r5
34 r5 = to_f32 r5
35 r5 = mul_f32 r5 r0
36 r6 = shr_i32 r7 16
37 r6 = bit_and r1 r6
38 r6 = to_f32 r6
39 r6 = mul_f32 r6 r0
40 r5 = fma_f32 r6 r10 r5
41 r5 = fma_f32 r5 r3 r4
42 r5 = trunc r5
43 r7 = shr_i32 r7 24
44 r7 = to_f32 r7
45 r7 = mul_f32 r7 r0
46 r9 = fma_f32 r7 r10 r9
47 r9 = fma_f32 r9 r3 r4
48 r9 = trunc r9
49 r9 = pack r5 r9 8
50 r9 = pack r8 r9 16
51 store32 arg(1) r9
I32 (Naive) 8888 over 8888
33 values (originally 33):
v0 = load32 arg(0)
↑ v1 = splat FF (3.5733111e-43)
v2 = bit_and v1 v0
v3 = load32 arg(1)
v4 = bit_and v1 v3
v5 = shr_i32 v0 24
↑ v6 = splat 100 (3.5873241e-43)
v7 = sub_i32 v6 v5
v8 = mul_i32 v4 v7
v9 = shr_i32 v8 8
v10 = add_i32 v2 v9
v11 = shr_i32 v0 8
v12 = bit_and v1 v11
v13 = shr_i32 v3 8
v14 = bit_and v1 v13
v15 = mul_i32 v14 v7
v16 = shr_i32 v15 8
v17 = add_i32 v12 v16
v18 = pack v10 v17 8
v19 = shr_i32 v0 16
v20 = bit_and v1 v19
v21 = shr_i32 v3 16
v22 = bit_and v1 v21
v23 = mul_i32 v22 v7
v24 = shr_i32 v23 8
v25 = add_i32 v20 v24
v26 = shr_i32 v3 24
v27 = mul_i32 v26 v7
v28 = shr_i32 v27 8
v29 = add_i32 v5 v28
v30 = pack v25 v29 8
v31 = pack v18 v30 16
store32 arg(1) v31
9 registers, 33 instructions:
0 r0 = splat FF (3.5733111e-43)
1 r1 = splat 100 (3.5873241e-43)
loop:
2 r2 = load32 arg(0)
3 r3 = bit_and r0 r2
4 r4 = load32 arg(1)
5 r5 = bit_and r0 r4
6 r6 = shr_i32 r2 24
7 r7 = sub_i32 r1 r6
8 r5 = mul_i32 r5 r7
9 r5 = shr_i32 r5 8
10 r5 = add_i32 r3 r5
11 r3 = shr_i32 r2 8
12 r3 = bit_and r0 r3
13 r8 = shr_i32 r4 8
14 r8 = bit_and r0 r8
15 r8 = mul_i32 r8 r7
16 r8 = shr_i32 r8 8
17 r8 = add_i32 r3 r8
18 r8 = pack r5 r8 8
19 r2 = shr_i32 r2 16
20 r2 = bit_and r0 r2
21 r5 = shr_i32 r4 16
22 r5 = bit_and r0 r5
23 r5 = mul_i32 r5 r7
24 r5 = shr_i32 r5 8
25 r5 = add_i32 r2 r5
26 r4 = shr_i32 r4 24
27 r7 = mul_i32 r4 r7
28 r7 = shr_i32 r7 8
29 r7 = add_i32 r6 r7
30 r7 = pack r5 r7 8
31 r7 = pack r8 r7 16
32 store32 arg(1) r7
I32 8888 over 8888
29 values (originally 29):
v0 = load32 arg(0)
↑ v1 = splat FF (3.5733111e-43)
v2 = bit_and v0 v1
v3 = load32 arg(1)
v4 = bit_and v3 v1
v5 = shr_i32 v0 24
↑ v6 = splat 100 (3.5873241e-43)
v7 = sub_i32 v6 v5
v8 = mul_i16x2 v4 v7
v9 = shr_i32 v8 8
v10 = add_i32 v2 v9
v11 = bytes v0 2
v12 = bytes v3 2
v13 = mul_i16x2 v12 v7
v14 = shr_i32 v13 8
v15 = add_i32 v11 v14
v16 = pack v10 v15 8
v17 = bytes v0 3
v18 = bytes v3 3
v19 = mul_i16x2 v18 v7
v20 = shr_i32 v19 8
v21 = add_i32 v17 v20
v22 = shr_i32 v3 24
v23 = mul_i16x2 v22 v7
v24 = shr_i32 v23 8
v25 = add_i32 v5 v24
v26 = pack v21 v25 8
v27 = pack v16 v26 16
store32 arg(1) v27
9 registers, 29 instructions:
0 r0 = splat FF (3.5733111e-43)
1 r1 = splat 100 (3.5873241e-43)
loop:
2 r2 = load32 arg(0)
3 r3 = bit_and r2 r0
4 r4 = load32 arg(1)
5 r5 = bit_and r4 r0
6 r6 = shr_i32 r2 24
7 r7 = sub_i32 r1 r6
8 r5 = mul_i16x2 r5 r7
9 r5 = shr_i32 r5 8
10 r5 = add_i32 r3 r5
11 r3 = bytes r2 2
12 r8 = bytes r4 2
13 r8 = mul_i16x2 r8 r7
14 r8 = shr_i32 r8 8
15 r8 = add_i32 r3 r8
16 r8 = pack r5 r8 8
17 r2 = bytes r2 3
18 r5 = bytes r4 3
19 r5 = mul_i16x2 r5 r7
20 r5 = shr_i32 r5 8
21 r5 = add_i32 r2 r5
22 r4 = shr_i32 r4 24
23 r7 = mul_i16x2 r4 r7
24 r7 = shr_i32 r7 8
25 r7 = add_i32 r6 r7
26 r7 = pack r5 r7 8
27 r7 = pack r8 r7 16
28 store32 arg(1) r7
I32 (SWAR) 8888 over 8888
15 values (originally 15):
v0 = load32 arg(0)
v1 = bytes v0 404
↑ v2 = splat 1000100 (2.3510604e-38)
v3 = sub_i16x2 v2 v1
v4 = load32 arg(1)
↑ v5 = splat FF00FF (2.3418409e-38)
v6 = bit_and v4 v5
v7 = mul_i16x2 v6 v3
v8 = shr_i16x2 v7 8
v9 = shr_i16x2 v4 8
v10 = mul_i16x2 v9 v3
v11 = bit_clear v10 v5
v12 = bit_or v8 v11
v13 = add_i32 v0 v12
store32 arg(1) v13
6 registers, 15 instructions:
0 r0 = splat 1000100 (2.3510604e-38)
1 r1 = splat FF00FF (2.3418409e-38)
loop:
2 r2 = load32 arg(0)
3 r3 = bytes r2 404
4 r3 = sub_i16x2 r0 r3
5 r4 = load32 arg(1)
6 r5 = bit_and r4 r1
7 r5 = mul_i16x2 r5 r3
8 r5 = shr_i16x2 r5 8
9 r4 = shr_i16x2 r4 8
10 r3 = mul_i16x2 r4 r3
11 r3 = bit_clear r3 r1
12 r3 = bit_or r5 r3
13 r3 = add_i32 r2 r3
14 store32 arg(1) r3
6 values (originally 6):
↟ v0 = splat 1 (1.4012985e-45)
↟ v1 = splat 2 (2.8025969e-45)
↑ v2 = add_i32 v0 v1
v3 = load32 arg(0)
v4 = mul_i32 v3 v2
store32 arg(0) v4
2 registers, 6 instructions:
0 r0 = splat 1 (1.4012985e-45)
1 r1 = splat 2 (2.8025969e-45)
2 r1 = add_i32 r0 r1
loop:
3 r0 = load32 arg(0)
4 r0 = mul_i32 r0 r1
5 store32 arg(0) r0
23 values (originally 23):
↑ v0 = splat FF (3.5733111e-43)
v1 = load32 arg(0)
v2 = bit_and v0 v1
v3 = load32 arg(1)
v4 = bit_and v0 v3
v5 = add_i32 v2 v4
v6 = shr_i32 v1 8
v7 = bit_and v0 v6
v8 = shr_i32 v3 8
v9 = bit_and v0 v8
v10 = add_i32 v7 v9
v11 = pack v5 v10 8
v12 = shr_i32 v1 16
v13 = bit_and v0 v12
v14 = shr_i32 v3 16
v15 = bit_and v0 v14
v16 = add_i32 v13 v15
v17 = shr_i32 v1 24
v18 = shr_i32 v3 24
v19 = add_i32 v17 v18
v20 = pack v16 v19 8
v21 = pack v11 v20 16
store32 arg(1) v21
6 registers, 23 instructions:
0 r0 = splat FF (3.5733111e-43)
loop:
1 r1 = load32 arg(0)
2 r2 = bit_and r0 r1
3 r3 = load32 arg(1)
4 r4 = bit_and r0 r3
5 r4 = add_i32 r2 r4
6 r2 = shr_i32 r1 8
7 r2 = bit_and r0 r2
8 r5 = shr_i32 r3 8
9 r5 = bit_and r0 r5
10 r5 = add_i32 r2 r5
11 r5 = pack r4 r5 8
12 r4 = shr_i32 r1 16
13 r4 = bit_and r0 r4
14 r2 = shr_i32 r3 16
15 r2 = bit_and r0 r2
16 r2 = add_i32 r4 r2
17 r1 = shr_i32 r1 24
18 r3 = shr_i32 r3 24
19 r3 = add_i32 r1 r3
20 r3 = pack r2 r3 8
21 r3 = pack r5 r3 16
22 store32 arg(1) r3