2010-02-04 20:36:58 +00:00
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// Copyright 2010 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// CPU specific code for arm independent of OS goes here.
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#include <sys/syscall.h>
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#include <unistd.h>
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#ifdef __mips
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#include <asm/cachectl.h>
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#endif // #ifdef __mips
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#include "v8.h"
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2010-05-17 15:41:35 +00:00
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#if defined(V8_TARGET_ARCH_MIPS)
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2010-02-04 20:36:58 +00:00
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#include "cpu.h"
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2011-03-28 13:05:36 +00:00
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#include "macro-assembler.h"
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#include "simulator.h" // For cache flushing.
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2010-02-04 20:36:58 +00:00
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namespace v8 {
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namespace internal {
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2011-03-28 13:05:36 +00:00
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2010-02-04 20:36:58 +00:00
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void CPU::Setup() {
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2011-03-28 13:05:36 +00:00
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CpuFeatures* cpu_features = Isolate::Current()->cpu_features();
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cpu_features->Probe(true);
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if (!cpu_features->IsSupported(FPU) || Serializer::enabled()) {
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V8::DisableCrankshaft();
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}
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2010-02-04 20:36:58 +00:00
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}
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2011-03-28 13:05:36 +00:00
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2010-02-04 20:36:58 +00:00
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void CPU::FlushICache(void* start, size_t size) {
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2011-03-28 13:05:36 +00:00
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#if !defined (USE_SIMULATOR)
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2010-02-04 20:36:58 +00:00
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int res;
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// See http://www.linux-mips.org/wiki/Cacheflush_Syscall
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res = syscall(__NR_cacheflush, start, size, ICACHE);
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if (res) {
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V8_Fatal(__FILE__, __LINE__, "Failed to flush the instruction cache");
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}
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2011-03-28 13:05:36 +00:00
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#else // USE_SIMULATOR.
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// Not generating mips instructions for C-code. This means that we are
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// building a mips emulator based target. We should notify the simulator
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// that the Icache was flushed.
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// None of this code ends up in the snapshot so there are no issues
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// around whether or not to generate the code when building snapshots.
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Simulator::FlushICache(Isolate::Current()->simulator_i_cache(), start, size);
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#endif // USE_SIMULATOR.
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2010-02-04 20:36:58 +00:00
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}
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void CPU::DebugBreak() {
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#ifdef __mips
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asm volatile("break");
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#endif // #ifdef __mips
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}
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2011-03-28 13:05:36 +00:00
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2010-02-04 20:36:58 +00:00
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} } // namespace v8::internal
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2010-05-17 15:41:35 +00:00
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#endif // V8_TARGET_ARCH_MIPS
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