336 lines
14 KiB
C
336 lines
14 KiB
C
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// Copyright 2012 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// This file is an internal atomic implementation for compiler-based
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// ThreadSanitizer. Use base/atomicops.h instead.
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#ifndef V8_ATOMICOPS_INTERNALS_TSAN_H_
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#define V8_ATOMICOPS_INTERNALS_TSAN_H_
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// This struct is not part of the public API of this module; clients may not
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// use it. (However, it's exported via BASE_EXPORT because clients implicitly
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// do use it at link time by inlining these functions.)
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// Features of this x86. Values may not be correct before main() is run,
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// but are set conservatively.
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struct AtomicOps_x86CPUFeatureStruct {
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bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
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// after acquire compare-and-swap.
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bool has_sse2; // Processor has SSE2.
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};
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extern struct AtomicOps_x86CPUFeatureStruct
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AtomicOps_Internalx86CPUFeatures;
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#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
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namespace v8 {
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namespace internal {
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#ifndef TSAN_INTERFACE_ATOMIC_H
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#define TSAN_INTERFACE_ATOMIC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef char __tsan_atomic8;
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typedef short __tsan_atomic16; // NOLINT
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typedef int __tsan_atomic32;
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typedef long __tsan_atomic64; // NOLINT
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typedef enum {
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__tsan_memory_order_relaxed = (1 << 0) + 100500,
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__tsan_memory_order_consume = (1 << 1) + 100500,
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__tsan_memory_order_acquire = (1 << 2) + 100500,
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__tsan_memory_order_release = (1 << 3) + 100500,
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__tsan_memory_order_acq_rel = (1 << 4) + 100500,
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__tsan_memory_order_seq_cst = (1 << 5) + 100500,
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} __tsan_memory_order;
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__tsan_atomic8 __tsan_atomic8_load(const volatile __tsan_atomic8* a,
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__tsan_memory_order mo);
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__tsan_atomic16 __tsan_atomic16_load(const volatile __tsan_atomic16* a,
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__tsan_memory_order mo);
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__tsan_atomic32 __tsan_atomic32_load(const volatile __tsan_atomic32* a,
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__tsan_memory_order mo);
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__tsan_atomic64 __tsan_atomic64_load(const volatile __tsan_atomic64* a,
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__tsan_memory_order mo);
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void __tsan_atomic8_store(volatile __tsan_atomic8* a, __tsan_atomic8 v,
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__tsan_memory_order mo);
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void __tsan_atomic16_store(volatile __tsan_atomic16* a, __tsan_atomic16 v,
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__tsan_memory_order mo);
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void __tsan_atomic32_store(volatile __tsan_atomic32* a, __tsan_atomic32 v,
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__tsan_memory_order mo);
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void __tsan_atomic64_store(volatile __tsan_atomic64* a, __tsan_atomic64 v,
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__tsan_memory_order mo);
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__tsan_atomic8 __tsan_atomic8_exchange(volatile __tsan_atomic8* a,
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__tsan_atomic8 v, __tsan_memory_order mo);
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__tsan_atomic16 __tsan_atomic16_exchange(volatile __tsan_atomic16* a,
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__tsan_atomic16 v, __tsan_memory_order mo);
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__tsan_atomic32 __tsan_atomic32_exchange(volatile __tsan_atomic32* a,
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__tsan_atomic32 v, __tsan_memory_order mo);
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__tsan_atomic64 __tsan_atomic64_exchange(volatile __tsan_atomic64* a,
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__tsan_atomic64 v, __tsan_memory_order mo);
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__tsan_atomic8 __tsan_atomic8_fetch_add(volatile __tsan_atomic8* a,
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__tsan_atomic8 v, __tsan_memory_order mo);
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__tsan_atomic16 __tsan_atomic16_fetch_add(volatile __tsan_atomic16* a,
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__tsan_atomic16 v, __tsan_memory_order mo);
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__tsan_atomic32 __tsan_atomic32_fetch_add(volatile __tsan_atomic32* a,
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__tsan_atomic32 v, __tsan_memory_order mo);
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__tsan_atomic64 __tsan_atomic64_fetch_add(volatile __tsan_atomic64* a,
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__tsan_atomic64 v, __tsan_memory_order mo);
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__tsan_atomic8 __tsan_atomic8_fetch_and(volatile __tsan_atomic8* a,
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__tsan_atomic8 v, __tsan_memory_order mo);
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__tsan_atomic16 __tsan_atomic16_fetch_and(volatile __tsan_atomic16* a,
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__tsan_atomic16 v, __tsan_memory_order mo);
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__tsan_atomic32 __tsan_atomic32_fetch_and(volatile __tsan_atomic32* a,
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__tsan_atomic32 v, __tsan_memory_order mo);
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__tsan_atomic64 __tsan_atomic64_fetch_and(volatile __tsan_atomic64* a,
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__tsan_atomic64 v, __tsan_memory_order mo);
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__tsan_atomic8 __tsan_atomic8_fetch_or(volatile __tsan_atomic8* a,
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__tsan_atomic8 v, __tsan_memory_order mo);
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__tsan_atomic16 __tsan_atomic16_fetch_or(volatile __tsan_atomic16* a,
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__tsan_atomic16 v, __tsan_memory_order mo);
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__tsan_atomic32 __tsan_atomic32_fetch_or(volatile __tsan_atomic32* a,
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__tsan_atomic32 v, __tsan_memory_order mo);
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__tsan_atomic64 __tsan_atomic64_fetch_or(volatile __tsan_atomic64* a,
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__tsan_atomic64 v, __tsan_memory_order mo);
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__tsan_atomic8 __tsan_atomic8_fetch_xor(volatile __tsan_atomic8* a,
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__tsan_atomic8 v, __tsan_memory_order mo);
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__tsan_atomic16 __tsan_atomic16_fetch_xor(volatile __tsan_atomic16* a,
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__tsan_atomic16 v, __tsan_memory_order mo);
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__tsan_atomic32 __tsan_atomic32_fetch_xor(volatile __tsan_atomic32* a,
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__tsan_atomic32 v, __tsan_memory_order mo);
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__tsan_atomic64 __tsan_atomic64_fetch_xor(volatile __tsan_atomic64* a,
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__tsan_atomic64 v, __tsan_memory_order mo);
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int __tsan_atomic8_compare_exchange_weak(volatile __tsan_atomic8* a,
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__tsan_atomic8* c, __tsan_atomic8 v, __tsan_memory_order mo);
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int __tsan_atomic16_compare_exchange_weak(volatile __tsan_atomic16* a,
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__tsan_atomic16* c, __tsan_atomic16 v, __tsan_memory_order mo);
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int __tsan_atomic32_compare_exchange_weak(volatile __tsan_atomic32* a,
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__tsan_atomic32* c, __tsan_atomic32 v, __tsan_memory_order mo);
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int __tsan_atomic64_compare_exchange_weak(volatile __tsan_atomic64* a,
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__tsan_atomic64* c, __tsan_atomic64 v, __tsan_memory_order mo);
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int __tsan_atomic8_compare_exchange_strong(volatile __tsan_atomic8* a,
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__tsan_atomic8* c, __tsan_atomic8 v, __tsan_memory_order mo);
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int __tsan_atomic16_compare_exchange_strong(volatile __tsan_atomic16* a,
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__tsan_atomic16* c, __tsan_atomic16 v, __tsan_memory_order mo);
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int __tsan_atomic32_compare_exchange_strong(volatile __tsan_atomic32* a,
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__tsan_atomic32* c, __tsan_atomic32 v, __tsan_memory_order mo);
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int __tsan_atomic64_compare_exchange_strong(volatile __tsan_atomic64* a,
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__tsan_atomic64* c, __tsan_atomic64 v, __tsan_memory_order mo);
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void __tsan_atomic_thread_fence(__tsan_memory_order mo);
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // #ifndef TSAN_INTERFACE_ATOMIC_H
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inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 cmp = old_value;
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__tsan_atomic32_compare_exchange_strong(ptr, &cmp, new_value,
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__tsan_memory_order_relaxed);
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return cmp;
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}
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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return __tsan_atomic32_exchange(ptr, new_value,
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__tsan_memory_order_relaxed);
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}
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inline Atomic32 Acquire_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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return __tsan_atomic32_exchange(ptr, new_value,
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__tsan_memory_order_acquire);
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}
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inline Atomic32 Release_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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return __tsan_atomic32_exchange(ptr, new_value,
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__tsan_memory_order_release);
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}
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inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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return increment + __tsan_atomic32_fetch_add(ptr, increment,
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__tsan_memory_order_relaxed);
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}
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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return increment + __tsan_atomic32_fetch_add(ptr, increment,
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__tsan_memory_order_acq_rel);
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}
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inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 cmp = old_value;
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__tsan_atomic32_compare_exchange_strong(ptr, &cmp, new_value,
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__tsan_memory_order_acquire);
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return cmp;
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}
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inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 cmp = old_value;
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__tsan_atomic32_compare_exchange_strong(ptr, &cmp, new_value,
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__tsan_memory_order_release);
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return cmp;
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}
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inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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__tsan_atomic32_store(ptr, value, __tsan_memory_order_relaxed);
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}
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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__tsan_atomic32_store(ptr, value, __tsan_memory_order_relaxed);
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__tsan_atomic_thread_fence(__tsan_memory_order_seq_cst);
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}
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inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
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__tsan_atomic32_store(ptr, value, __tsan_memory_order_release);
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}
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inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
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return __tsan_atomic32_load(ptr, __tsan_memory_order_relaxed);
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}
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inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
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return __tsan_atomic32_load(ptr, __tsan_memory_order_acquire);
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}
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inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
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__tsan_atomic_thread_fence(__tsan_memory_order_seq_cst);
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return __tsan_atomic32_load(ptr, __tsan_memory_order_relaxed);
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}
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inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 cmp = old_value;
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__tsan_atomic64_compare_exchange_strong(ptr, &cmp, new_value,
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__tsan_memory_order_relaxed);
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return cmp;
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}
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inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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return __tsan_atomic64_exchange(ptr, new_value, __tsan_memory_order_relaxed);
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}
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inline Atomic64 Acquire_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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return __tsan_atomic64_exchange(ptr, new_value, __tsan_memory_order_acquire);
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}
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inline Atomic64 Release_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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return __tsan_atomic64_exchange(ptr, new_value, __tsan_memory_order_release);
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}
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inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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return increment + __tsan_atomic64_fetch_add(ptr, increment,
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__tsan_memory_order_relaxed);
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}
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inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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return increment + __tsan_atomic64_fetch_add(ptr, increment,
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__tsan_memory_order_acq_rel);
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}
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inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
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__tsan_atomic64_store(ptr, value, __tsan_memory_order_relaxed);
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}
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inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
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__tsan_atomic64_store(ptr, value, __tsan_memory_order_relaxed);
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__tsan_atomic_thread_fence(__tsan_memory_order_seq_cst);
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}
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inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
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__tsan_atomic64_store(ptr, value, __tsan_memory_order_release);
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}
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inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
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return __tsan_atomic64_load(ptr, __tsan_memory_order_relaxed);
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}
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inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
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return __tsan_atomic64_load(ptr, __tsan_memory_order_acquire);
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}
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inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
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__tsan_atomic_thread_fence(__tsan_memory_order_seq_cst);
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return __tsan_atomic64_load(ptr, __tsan_memory_order_relaxed);
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}
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inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 cmp = old_value;
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__tsan_atomic64_compare_exchange_strong(ptr, &cmp, new_value,
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__tsan_memory_order_acquire);
|
||
|
|
return cmp;
|
||
|
|
}
|
||
|
|
|
||
|
|
inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
|
||
|
|
Atomic64 old_value,
|
||
|
|
Atomic64 new_value) {
|
||
|
|
Atomic64 cmp = old_value;
|
||
|
|
__tsan_atomic64_compare_exchange_strong(ptr, &cmp, new_value,
|
||
|
|
__tsan_memory_order_release);
|
||
|
|
return cmp;
|
||
|
|
}
|
||
|
|
|
||
|
|
inline void MemoryBarrier() {
|
||
|
|
__tsan_atomic_thread_fence(__tsan_memory_order_seq_cst);
|
||
|
|
}
|
||
|
|
|
||
|
|
} // namespace internal
|
||
|
|
} // namespace v8
|
||
|
|
|
||
|
|
#undef ATOMICOPS_COMPILER_BARRIER
|
||
|
|
|
||
|
|
#endif // V8_ATOMICOPS_INTERNALS_TSAN_H_
|